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fix(core): PLL_DSI_NDIV wrongly set for DISC2

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The PLL_DSI_NDIV macro has been redefined to be calculated out of the other PLL_DSI parameters and the HSE_VALUE.

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This commit is contained in:
bleska
2026-02-11 22:43:06 +01:00
parent a10866988a
commit 4e19779310
3 changed files with 6 additions and 9 deletions
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5
core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h
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@@ -28,9 +28,8 @@
// PLL_DSI_ODF) / 8
#define DSI_LANE_BYTE_CLOCK_HZ 62000000UL // PLL DSI
#define PLL_DSI_IDF 4
// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
// * HSE_VALUE)
#define PLL_DSI_NDIV 62
#define PLL_DSI_NDIV \
((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
#define PLL_DSI_ODF 2
#define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
#define DSI_TX_ESCAPE_CLK_DIV 4 // 15.5MHz, ~7.75MHz (in LP)

5
core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h
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@@ -31,9 +31,8 @@
// PLL_DSI_ODF) / 8
#define DSI_LANE_BYTE_CLOCK_HZ 62000000UL // PLL DSI
#define PLL_DSI_IDF 4
// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
// * HSE_VALUE)
#define PLL_DSI_NDIV 62
#define PLL_DSI_NDIV \
((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
#define PLL_DSI_ODF 2
#define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
#define DSI_TX_ESCAPE_CLK_DIV 4 // 15.5MHz, ~7.75MHz (in LP)

5
core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h
View File

@@ -28,9 +28,8 @@
// PLL_DSI_ODF) / 8
#define DSI_LANE_BYTE_CLOCK_HZ 62000000UL // PLL DSI
#define PLL_DSI_IDF 4
// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
// * HSE_VALUE)
#define PLL_DSI_NDIV 62
#define PLL_DSI_NDIV \
((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
#define PLL_DSI_ODF 2
#define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
#define DSI_TX_ESCAPE_CLK_DIV 4 // 15.5MHz, ~7.75MHz (in LP)