diff --git a/core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h b/core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h
index eff4aeae9a..83d27269d6 100644
--- a/core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h
+++ b/core/embed/io/display/ltdc_dsi/panels/lx200d2406a/lx200d2406a.h
@@ -28,9 +28,8 @@
 // PLL_DSI_ODF) / 8
 #define DSI_LANE_BYTE_CLOCK_HZ 62000000UL  // PLL DSI
 #define PLL_DSI_IDF 4
-// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
-// * HSE_VALUE)
-#define PLL_DSI_NDIV 62
+#define PLL_DSI_NDIV \
+  ((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
 #define PLL_DSI_ODF 2
 #define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
 #define DSI_TX_ESCAPE_CLK_DIV 4  // 15.5MHz, ~7.75MHz (in LP)
diff --git a/core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h b/core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h
index 80b14d537a..ba1cd0b9bb 100644
--- a/core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h
+++ b/core/embed/io/display/ltdc_dsi/panels/lx250a2401a/lx250a2401a.h
@@ -31,9 +31,8 @@
 // PLL_DSI_ODF) / 8
 #define DSI_LANE_BYTE_CLOCK_HZ 62000000UL  // PLL DSI
 #define PLL_DSI_IDF 4
-// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
-// * HSE_VALUE)
-#define PLL_DSI_NDIV 62
+#define PLL_DSI_NDIV \
+  ((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
 #define PLL_DSI_ODF 2
 #define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
 #define DSI_TX_ESCAPE_CLK_DIV 4  // 15.5MHz, ~7.75MHz (in LP)
diff --git a/core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h b/core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h
index d68f0c83ee..f79d753d82 100644
--- a/core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h
+++ b/core/embed/io/display/ltdc_dsi/panels/stm32u5a9j-dk/stm32u5a9j-dk.h
@@ -28,9 +28,8 @@
 // PLL_DSI_ODF) / 8
 #define DSI_LANE_BYTE_CLOCK_HZ 62000000UL  // PLL DSI
 #define PLL_DSI_IDF 4
-// PLL_DSI_NDIV = (DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2
-// * HSE_VALUE)
-#define PLL_DSI_NDIV 62
+#define PLL_DSI_NDIV \
+  ((DSI_LANE_BYTE_CLOCK_HZ * 8 * PLL_DSI_ODF * PLL_DSI_IDF) / (2 * HSE_VALUE))
 #define PLL_DSI_ODF 2
 #define DSI_DPHY_FRANGE DSI_DPHY_FRANGE_450MHZ_510MHZ
 #define DSI_TX_ESCAPE_CLK_DIV 4  // 15.5MHz, ~7.75MHz (in LP)