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Updated Clocking (markdown)

mossmann
2012-05-01 09:30:06 -07:00
parent 3588d67a36
commit f35bdfeb1e
1 changed files with 12 additions and 1 deletions
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13
Clocking.md

@@ -8,9 +8,20 @@ HackRF clock signals are generated by the Si5351. The plan so far:
* A clock at quadruple the MAX5864 rate will be delivered to the CPLD.
* LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work)
Lemondrop+Jellybean Si5351 output mapping:
* CLK0 -> MAX2837
* CLK1 -> MAX5864/CPLD
* CLK2 -> CPLD
* CLK3 -> CPLD
* CLK4 -> LPC4330
* CLK5 -> RFFC5071
* CLK6 -> extra
* CLK7 -> extra
Future Si5351 output mapping:
* CLK0 -> MAX5864
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> CPLD
* CLK3 -> external clock output