diff --git a/Clocking.md b/Clocking.md
index d9dc848..0c41545 100644
--- a/Clocking.md
+++ b/Clocking.md
@@ -8,9 +8,20 @@ HackRF clock signals are generated by the Si5351.  The plan so far:
 * A clock at quadruple the MAX5864 rate will be delivered to the CPLD.
 * LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work)
 
+Lemondrop+Jellybean Si5351 output mapping:
+
+* CLK0 -> MAX2837
+* CLK1 -> MAX5864/CPLD
+* CLK2 -> CPLD
+* CLK3 -> CPLD
+* CLK4 -> LPC4330
+* CLK5 -> RFFC5071
+* CLK6 -> extra
+* CLK7 -> extra
+
 Future Si5351 output mapping:
 
-* CLK0 -> MAX5864
+* CLK0 -> MAX5864/CPLD
 * CLK1 -> CPLD
 * CLK2 -> CPLD
 * CLK3 -> external clock output