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Updated Clocking (markdown)
12
Clocking.md
12
Clocking.md
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HackRF clock signals are generated by the Si5351. The plan so far:
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crystal frequency: 25 MHz (supports 25 or 27 MHz)
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recommended clock input frequency: 10 MHz (supports 10 to 40 MHz, or higher with division)
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VCO frequency: 800 MHz (supports 600 to 900 MHz)
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MAX2837 clock: 40 MHz
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preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
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LPC4330 clock: 20 MHz (from integer-only output)
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* crystal frequency: 25 MHz (supports 25 or 27 MHz)
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* recommended clock input frequency: 10 MHz (supports 10 to 40 MHz, or higher with division)
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* VCO frequency: 800 MHz (supports 600 to 900 MHz)
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* MAX2837 clock: 40 MHz
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* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
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* LPC4330 clock: 20 MHz (from integer-only output)
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A DDR clock at double the MAX5864 will be delivered to the CPLD.
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