From ad64c66fc5f0fe68968baeb5d210378d4adc8e46 Mon Sep 17 00:00:00 2001 From: mossmann Date: Tue, 17 Apr 2012 15:00:21 -0700 Subject: [PATCH] Updated Clocking (markdown) --- Clocking.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Clocking.md b/Clocking.md index 8bf86c3..e796c96 100644 --- a/Clocking.md +++ b/Clocking.md @@ -1,10 +1,10 @@ HackRF clock signals are generated by the Si5351. The plan so far: -crystal frequency: 25 MHz (supports 25 or 27 MHz) -recommended clock input frequency: 10 MHz (supports 10 to 40 MHz, or higher with division) -VCO frequency: 800 MHz (supports 600 to 900 MHz) -MAX2837 clock: 40 MHz -preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz -LPC4330 clock: 20 MHz (from integer-only output) +* crystal frequency: 25 MHz (supports 25 or 27 MHz) +* recommended clock input frequency: 10 MHz (supports 10 to 40 MHz, or higher with division) +* VCO frequency: 800 MHz (supports 600 to 900 MHz) +* MAX2837 clock: 40 MHz +* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz +* LPC4330 clock: 20 MHz (from integer-only output) A DDR clock at double the MAX5864 will be delivered to the CPLD. \ No newline at end of file