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Updated Clocking (markdown)

mossmann
2012-04-30 22:36:21 -07:00
parent d54cb4fa96
commit a797ff1745
1 changed files with 8 additions and 8 deletions
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16
Clocking.md

@@ -10,11 +10,11 @@ HackRF clock signals are generated by the Si5351. The plan so far:
Future Si5351 output mapping:
CLK0 -> none
CLK1 -> none
CLK2 -> RFFC5071
CLK3 -> MAX2837
CLK4 -> MAX5864
CLK5 -> external clock output
CLK6 -> CPLD
CLK7 -> CPLD
* CLK0 -> none
* CLK1 -> none
* CLK2 -> RFFC5071
* CLK3 -> MAX2837
* CLK4 -> MAX5864
* CLK5 -> external clock output
* CLK6 -> CPLD
* CLK7 -> CPLD