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Updated Clocking (markdown)

mossmann
2012-04-17 15:04:15 -07:00
parent ad64c66fc5
commit 38a5211f89
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Clocking.md

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HackRF clock signals are generated by the Si5351. The plan so far:
* crystal frequency: 25 MHz (supports 25 or 27 MHz)
* recommended clock input frequency: 10 MHz (supports 10 to 40 MHz, or higher with division)
* optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division)
* VCO frequency: 800 MHz (supports 600 to 900 MHz)
* MAX2837 clock: 40 MHz
* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
* LPC4330 clock: 20 MHz (from integer-only output)
* A DDR clock at double the MAX5864 will be delivered to the CPLD.
* LPC43xx clock: 20 MHz (from integer-only output)
A DDR clock at double the MAX5864 will be delivered to the CPLD.
The LPC43xx will start up on its internal RC oscillator, activate the Si5351, and then switch to the 20 MHz clock coming from the Si5351.