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firmware: replace static gpio & scu definitions

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This commit is contained in:
Antoine van Gelder
2026-03-07 10:44:34 +00:00
parent 5d8e23953b
commit ce5cd7b052
22 changed files with 497 additions and 994 deletions
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581
firmware/common/hackrf_core.c
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@@ -24,24 +24,17 @@
#include "hackrf_core.h"
#include "hackrf_ui.h"
#include "delay.h"
#include "sgpio.h"
#include "si5351c.h"
#include "spi_ssp.h"
#include "max283x.h"
#include "max5864.h"
#include "max5864_target.h"
#include "w25q80bv.h"
#include "w25q80bv_target.h"
#include "i2c_bus.h"
#include "i2c_lpc.h"
#include "cpld_jtag.h"
#include "ice40_spi.h"
#include "platform_detect.h"
#include "platform_gpio.h"
#include "platform_scu.h"
#include "clkin.h"
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/lpc43xx/ccu.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/ssp.h>
#if (defined HACKRF_ONE || defined PRALINE)
#include "portapack.h"
@@ -49,152 +42,6 @@
#include "gpio_lpc.h"
/* GPIO Output PinMux */
static struct gpio gpio_led[] = {
GPIO(2, 1),
GPIO(2, 2),
GPIO(2, 8),
#ifdef RAD1O
GPIO(5, 26),
#endif
#ifdef PRALINE
GPIO(4, 6),
#endif
};
// clang-format off
#ifndef PRALINE
static struct gpio gpio_1v8_enable = GPIO(3, 6);
#else
static struct gpio gpio_1v2_enable = GPIO(4, 7);
static struct gpio gpio_3v3aux_enable_n = GPIO(5, 15);
#endif
/* MAX283x GPIO (XCVR_CTL / CS_XCVR) PinMux */
#ifdef PRALINE
static struct gpio gpio_max283x_select = GPIO(6, 28);
#else
static struct gpio gpio_max283x_select = GPIO(0, 15);
#endif
/* MAX5864 SPI chip select (AD_CS / CS_AD) GPIO PinMux */
#ifdef PRALINE
static struct gpio gpio_max5864_select = GPIO(6, 30);
#else
static struct gpio gpio_max5864_select = GPIO(2, 7);
#endif
/* RFFC5071 GPIO serial interface PinMux */
// #ifdef RAD1O
// static struct gpio gpio_rffc5072_select = GPIO(2, 13);
// static struct gpio gpio_rffc5072_clock = GPIO(5, 6);
// static struct gpio gpio_rffc5072_data = GPIO(3, 3);
// static struct gpio gpio_rffc5072_reset = GPIO(2, 14);
// #endif
/* RF supply (VAA) control */
#ifdef HACKRF_ONE
static struct gpio gpio_vaa_disable = GPIO(2, 9);
#endif
#ifdef PRALINE
static struct gpio gpio_vaa_disable = GPIO(4, 1);
#endif
#ifdef RAD1O
static struct gpio gpio_vaa_enable = GPIO(2, 9);
#endif
static struct gpio gpio_w25q80bv_hold = GPIO(1, 14);
static struct gpio gpio_w25q80bv_wp = GPIO(1, 15);
static struct gpio gpio_w25q80bv_select = GPIO(5, 11);
/* RF switch control */
#ifdef HACKRF_ONE
static struct gpio gpio_hp = GPIO(2, 0);
static struct gpio gpio_lp = GPIO(2, 10);
static struct gpio gpio_tx_mix_bp = GPIO(2, 11);
static struct gpio gpio_no_mix_bypass = GPIO(1, 0);
static struct gpio gpio_rx_mix_bp = GPIO(2, 12);
static struct gpio gpio_tx_amp = GPIO(2, 15);
static struct gpio gpio_tx = GPIO(5, 15);
static struct gpio gpio_mix_bypass = GPIO(5, 16);
static struct gpio gpio_rx = GPIO(5, 5);
static struct gpio gpio_no_tx_amp_pwr = GPIO(3, 5);
static struct gpio gpio_amp_bypass = GPIO(0, 14);
static struct gpio gpio_rx_amp = GPIO(1, 11);
static struct gpio gpio_no_rx_amp_pwr = GPIO(1, 12);
#endif
#ifdef RAD1O
static struct gpio gpio_tx_rx_n = GPIO(1, 11);
static struct gpio gpio_tx_rx = GPIO(0, 14);
static struct gpio gpio_by_mix = GPIO(1, 12);
static struct gpio gpio_by_mix_n = GPIO(2, 10);
static struct gpio gpio_by_amp = GPIO(1, 0);
static struct gpio gpio_by_amp_n = GPIO(5, 5);
static struct gpio gpio_mixer_en = GPIO(5, 16);
static struct gpio gpio_low_high_filt = GPIO(2, 11);
static struct gpio gpio_low_high_filt_n = GPIO(2, 12);
static struct gpio gpio_tx_amp = GPIO(2, 15);
static struct gpio gpio_rx_lna = GPIO(5, 15);
#endif
#ifdef PRALINE
static struct gpio gpio_tx_en = GPIO(3, 4);
static struct gpio gpio_mix_en_n = GPIO(3, 2);
static struct gpio gpio_mix_en_n_r1_0 = GPIO(5, 6);
static struct gpio gpio_lpf_en = GPIO(4, 8);
static struct gpio gpio_rf_amp_en = GPIO(4, 9);
static struct gpio gpio_ant_bias_en_n = GPIO(1, 12);
#endif
/* CPLD JTAG interface GPIO pins, FPGA config pins in Praline */
static struct gpio gpio_cpld_tck = GPIO(3, 0);
#ifdef PRALINE
static struct gpio gpio_fpga_cfg_creset = GPIO(2, 11);
static struct gpio gpio_fpga_cfg_cdone = GPIO(5, 14);
static struct gpio gpio_fpga_cfg_spi_cs = GPIO(2, 10);
#else
static struct gpio gpio_cpld_tdo = GPIO(5, 18);
#if (defined HACKRF_ONE || defined RAD1O)
static struct gpio gpio_cpld_tms = GPIO(3, 4);
static struct gpio gpio_cpld_tdi = GPIO(3, 1);
#else
static struct gpio gpio_cpld_tms = GPIO(3, 1);
static struct gpio gpio_cpld_tdi = GPIO(3, 4);
#endif
#endif
#if (defined HACKRF_ONE || defined PRALINE)
static struct gpio gpio_cpld_pp_tms = GPIO(1, 1);
static struct gpio gpio_cpld_pp_tdo = GPIO(1, 8);
#endif
/* other CPLD interface GPIO pins */
#ifndef PRALINE
static struct gpio gpio_trigger_enable = GPIO(5, 12);
#endif
static struct gpio gpio_q_invert = GPIO(0, 13);
/* HackRF One r9 */
#ifdef HACKRF_ONE
static struct gpio gpio_h1r9_rx = GPIO(0, 7);
static struct gpio gpio_h1r9_1v8_enable = GPIO(2, 9);
static struct gpio gpio_h1r9_vaa_disable = GPIO(3, 6);
static struct gpio gpio_h1r9_trigger_enable = GPIO(5, 5);
#endif
#ifdef PRALINE
static struct gpio gpio_p2_ctrl0 = GPIO(7, 3);
static struct gpio gpio_p2_ctrl1 = GPIO(7, 4);
static struct gpio gpio_p1_ctrl0 = GPIO(0, 14);
static struct gpio gpio_p1_ctrl1 = GPIO(5, 16);
static struct gpio gpio_p1_ctrl2 = GPIO(3, 5);
static struct gpio gpio_clkin_ctrl = GPIO(0, 15);
static struct gpio gpio_aa_en = GPIO(1, 7);
static struct gpio gpio_trigger_in = GPIO(6, 26);
static struct gpio gpio_trigger_out = GPIO(5, 6);
static struct gpio gpio_pps_out = GPIO(5, 5);
#endif
// clang-format on
i2c_bus_t i2c0 = {
.obj = (void*) I2C0_BASE,
.start = i2c_lpc_start,
@@ -222,6 +69,33 @@ si5351c_driver_t clock_gen = {
.i2c_address = 0x60,
};
static ssp_config_t ssp_config_max283x = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
};
max283x_driver_t max283x = {};
static ssp_config_t ssp_config_max5864 = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.data_bits = SSP_DATA_8BITS,
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
};
spi_bus_t spi_bus_ssp1 = {
.obj = (void*) SSP1_BASE,
.config = &ssp_config_max5864,
@@ -231,62 +105,15 @@ spi_bus_t spi_bus_ssp1 = {
.transfer_gather = spi_ssp_transfer_gather,
};
#ifdef PRALINE
const ssp_config_t ssp_config_max283x = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.data_bits = SSP_DATA_9BITS, // send 2 words
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
.gpio_select = &gpio_max283x_select,
};
#else
const ssp_config_t ssp_config_max283x = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.data_bits = SSP_DATA_16BITS,
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
.gpio_select = &gpio_max283x_select,
};
#endif
max283x_driver_t max283x = {};
const ssp_config_t ssp_config_max5864 = {
/* FIXME speed up once everything is working reliably */
/*
// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
const uint8_t serial_clock_rate = 32;
const uint8_t clock_prescale_rate = 128;
*/
// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
.data_bits = SSP_DATA_8BITS,
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
.gpio_select = &gpio_max5864_select,
};
max5864_driver_t max5864 = {
.bus = &spi_bus_ssp1,
.target_init = max5864_target_init,
};
const ssp_config_t ssp_config_w25q80bv = {
ssp_config_t ssp_config_w25q80bv = {
.data_bits = SSP_DATA_8BITS,
.serial_clock_rate = 2,
.clock_prescale_rate = 2,
.gpio_select = &gpio_w25q80bv_select,
};
spi_bus_t spi_bus_ssp0 = {
@@ -300,33 +127,23 @@ spi_bus_t spi_bus_ssp0 = {
w25q80bv_driver_t spi_flash = {
.bus = &spi_bus_ssp0,
.gpio_hold = &gpio_w25q80bv_hold,
.gpio_wp = &gpio_w25q80bv_wp,
.target_init = w25q80bv_target_init,
};
sgpio_config_t sgpio_config = {
.gpio_q_invert = &gpio_q_invert,
#ifndef PRALINE
.gpio_trigger_enable = &gpio_trigger_enable,
#endif
.slice_mode_multislice = true,
};
#ifdef PRALINE
const ssp_config_t ssp_config_ice40_fpga = {
ssp_config_t ssp_config_ice40_fpga = {
.data_bits = SSP_DATA_8BITS,
.spi_mode = SSP_CPOL_1_CPHA_1,
.serial_clock_rate = 21,
.clock_prescale_rate = 2,
.gpio_select = &gpio_fpga_cfg_spi_cs,
};
ice40_spi_driver_t ice40 = {
.bus = &spi_bus_ssp1,
.gpio_select = &gpio_fpga_cfg_spi_cs,
.gpio_creset = &gpio_fpga_cfg_creset,
.gpio_cdone = &gpio_fpga_cfg_cdone,
};
fpga_driver_t fpga = {
@@ -340,55 +157,9 @@ radio_t radio = {
rf_path_t rf_path = {
.switchctrl = 0,
#ifdef HACKRF_ONE
.gpio_hp = &gpio_hp,
.gpio_lp = &gpio_lp,
.gpio_tx_mix_bp = &gpio_tx_mix_bp,
.gpio_no_mix_bypass = &gpio_no_mix_bypass,
.gpio_rx_mix_bp = &gpio_rx_mix_bp,
.gpio_tx_amp = &gpio_tx_amp,
.gpio_tx = &gpio_tx,
.gpio_mix_bypass = &gpio_mix_bypass,
.gpio_rx = &gpio_rx,
.gpio_no_tx_amp_pwr = &gpio_no_tx_amp_pwr,
.gpio_amp_bypass = &gpio_amp_bypass,
.gpio_rx_amp = &gpio_rx_amp,
.gpio_no_rx_amp_pwr = &gpio_no_rx_amp_pwr,
#endif
#ifdef RAD1O
.gpio_tx_rx_n = &gpio_tx_rx_n,
.gpio_tx_rx = &gpio_tx_rx,
.gpio_by_mix = &gpio_by_mix,
.gpio_by_mix_n = &gpio_by_mix_n,
.gpio_by_amp = &gpio_by_amp,
.gpio_by_amp_n = &gpio_by_amp_n,
.gpio_mixer_en = &gpio_mixer_en,
.gpio_low_high_filt = &gpio_low_high_filt,
.gpio_low_high_filt_n = &gpio_low_high_filt_n,
.gpio_tx_amp = &gpio_tx_amp,
.gpio_rx_lna = &gpio_rx_lna,
#endif
#ifdef PRALINE
.gpio_tx_en = &gpio_tx_en,
.gpio_mix_en_n = &gpio_mix_en_n,
.gpio_lpf_en = &gpio_lpf_en,
.gpio_rf_amp_en = &gpio_rf_amp_en,
.gpio_ant_bias_en_n = &gpio_ant_bias_en_n,
#endif
};
jtag_gpio_t jtag_gpio_cpld = {
.gpio_tck = &gpio_cpld_tck,
#ifndef PRALINE
.gpio_tms = &gpio_cpld_tms,
.gpio_tdi = &gpio_cpld_tdi,
.gpio_tdo = &gpio_cpld_tdo,
#endif
#if (defined HACKRF_ONE || defined PRALINE)
.gpio_pp_tms = &gpio_cpld_pp_tms,
.gpio_pp_tdo = &gpio_cpld_pp_tdo,
#endif
};
jtag_gpio_t jtag_gpio_cpld = {};
jtag_t jtag_cpld = {
.gpio = &jtag_gpio_cpld,
@@ -892,6 +663,9 @@ void ssp1_set_mode_ice40(void)
void pin_shutdown(void)
{
const platform_gpio_t* gpio = platform_gpio();
const platform_scu_t* scu = platform_scu();
/* Configure all GPIO as Input (safe state) */
gpio_init();
@@ -910,50 +684,50 @@ void pin_shutdown(void)
* LPC43xx pull-up and pull-down resistors are approximately 53K.
*/
#if (defined HACKRF_ONE || defined PRALINE)
scu_pinmux(SCU_PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_PP_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_PP_TMS, SCU_GPIO_PUP | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_PP_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
#endif
scu_pinmux(SCU_PINMUX_CPLD_TCK, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_CPLD_TCK, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
#ifndef PRALINE
scu_pinmux(SCU_PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_CPLD_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION4);
scu_pinmux(scu->PINMUX_CPLD_TMS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_CPLD_TDI, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_CPLD_TDO, SCU_GPIO_PDN | SCU_CONF_FUNCTION4);
#endif
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_LED1, SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_LED2, SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_LED3, SCU_GPIO_NOPULL);
#ifdef RAD1O
scu_pinmux(SCU_PINMUX_LED4, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
scu_pinmux(scu->PINMUX_LED4, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION4);
#endif
#ifdef PRALINE
scu_pinmux(SCU_PINMUX_LED4, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_LED4, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
#endif
/* Configure USB indicators */
#ifdef JAWBREAKER
scu_pinmux(SCU_PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
scu_pinmux(SCU_PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
scu_pinmux(scu->PINMUX_USB_LED0, SCU_CONF_FUNCTION3);
scu_pinmux(scu->PINMUX_USB_LED1, SCU_CONF_FUNCTION3);
#endif
#ifdef PRALINE
disable_1v2_power();
disable_3v3aux_power();
gpio_output(&gpio_1v2_enable);
gpio_output(&gpio_3v3aux_enable_n);
scu_pinmux(SCU_PINMUX_EN1V2, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_EN3V3_AUX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
gpio_output(gpio->gpio_1v2_enable);
gpio_output(gpio->gpio_3v3aux_enable_n);
scu_pinmux(scu->PINMUX_EN1V2, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_EN3V3_AUX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
#else
disable_1v8_power();
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
#ifdef HACKRF_ONE
gpio_output(&gpio_h1r9_1v8_enable);
scu_pinmux(SCU_H1R9_EN1V8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_output(gpio->h1r9_1v8_enable);
scu_pinmux(scu->H1R9_EN1V8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
#endif
} else {
gpio_output(&gpio_1v8_enable);
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_output(gpio->gpio_1v8_enable);
scu_pinmux(scu->PINMUX_EN1V8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
}
#endif
@@ -964,10 +738,10 @@ void pin_shutdown(void)
/* Configure RF power supply (VAA) switch control signal as output */
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
#ifdef HACKRF_ONE
gpio_output(&gpio_h1r9_vaa_disable);
gpio_output(gpio->h1r9_vaa_disable);
#endif
} else {
gpio_output(&gpio_vaa_disable);
gpio_output(gpio->vaa_disable);
}
#endif
@@ -976,51 +750,51 @@ void pin_shutdown(void)
disable_rf_power();
/* Configure RF power supply (VAA) switch control signal as output */
gpio_output(&gpio_vaa_enable);
gpio_output(gpio->vaa_enable);
/* Disable unused clock outputs. They generate noise. */
scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7);
scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7);
scu_pinmux(SCU_PINMUX_GPIO3_10, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_GPIO3_11, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_10, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_11, SCU_GPIO_PDN | SCU_CONF_FUNCTION0);
#endif
#ifdef PRALINE
scu_pinmux(SCU_P2_CTRL0, SCU_P2_CTRL0_PINCFG);
scu_pinmux(SCU_P2_CTRL1, SCU_P2_CTRL1_PINCFG);
scu_pinmux(SCU_P1_CTRL0, SCU_P1_CTRL0_PINCFG);
scu_pinmux(SCU_P1_CTRL1, SCU_P1_CTRL1_PINCFG);
scu_pinmux(SCU_P1_CTRL2, SCU_P1_CTRL2_PINCFG);
scu_pinmux(SCU_CLKIN_CTRL, SCU_CLKIN_CTRL_PINCFG);
scu_pinmux(SCU_AA_EN, SCU_AA_EN_PINCFG);
scu_pinmux(SCU_TRIGGER_IN, SCU_TRIGGER_IN_PINCFG);
scu_pinmux(SCU_TRIGGER_OUT, SCU_TRIGGER_OUT_PINCFG);
scu_pinmux(SCU_PPS_OUT, SCU_PPS_OUT_PINCFG);
scu_pinmux(SCU_PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->P2_CTRL0, scu->P2_CTRL0_PINCFG);
scu_pinmux(scu->P2_CTRL1, scu->P2_CTRL1_PINCFG);
scu_pinmux(scu->P1_CTRL0, scu->P1_CTRL0_PINCFG);
scu_pinmux(scu->P1_CTRL1, scu->P1_CTRL1_PINCFG);
scu_pinmux(scu->P1_CTRL2, scu->P1_CTRL2_PINCFG);
scu_pinmux(scu->CLKIN_CTRL, scu->CLKIN_CTRL_PINCFG);
scu_pinmux(scu->AA_EN, scu->AA_EN_PINCFG);
scu_pinmux(scu->TRIGGER_IN, scu->TRIGGER_IN_PINCFG);
scu_pinmux(scu->TRIGGER_OUT, scu->TRIGGER_OUT_PINCFG);
scu_pinmux(scu->PPS_OUT, scu->PPS_OUT_PINCFG);
scu_pinmux(scu->PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
scu_pinmux(scu->PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
p2_ctrl_set(P2_SIGNAL_CLK3);
p1_ctrl_set(P1_SIGNAL_CLKIN);
narrowband_filter_set(0);
clkin_ctrl_set(CLKIN_SIGNAL_P22);
gpio_output(&gpio_p2_ctrl0);
gpio_output(&gpio_p2_ctrl1);
gpio_output(&gpio_p1_ctrl0);
gpio_output(&gpio_p1_ctrl1);
gpio_output(&gpio_p1_ctrl2);
gpio_output(&gpio_clkin_ctrl);
gpio_output(&gpio_pps_out);
gpio_output(&gpio_aa_en);
gpio_input(&gpio_trigger_in);
gpio_input(&gpio_trigger_out);
gpio_clear(&gpio_fpga_cfg_spi_cs);
gpio_output(&gpio_fpga_cfg_spi_cs);
gpio_clear(&gpio_fpga_cfg_creset);
gpio_output(&gpio_fpga_cfg_creset);
gpio_input(&gpio_fpga_cfg_cdone);
gpio_output(gpio->p2_ctrl0);
gpio_output(gpio->p2_ctrl1);
gpio_output(gpio->p1_ctrl0);
gpio_output(gpio->p1_ctrl1);
gpio_output(gpio->p1_ctrl2);
gpio_output(gpio->clkin_ctrl);
gpio_output(gpio->pps_out);
gpio_output(gpio->aa_en);
gpio_input(gpio->trigger_in);
gpio_input(gpio->trigger_out);
gpio_clear(gpio->fpga_cfg_spi_cs);
gpio_output(gpio->fpga_cfg_spi_cs);
gpio_clear(gpio->fpga_cfg_creset);
gpio_output(gpio->fpga_cfg_creset);
gpio_input(gpio->fpga_cfg_cdone);
#endif
/* enable input on SCL and SDA pins */
@@ -1030,6 +804,9 @@ void pin_shutdown(void)
/* Run after pin_shutdown() and prior to enabling power supplies. */
void pin_setup(void)
{
const platform_gpio_t* gpio = platform_gpio();
const platform_scu_t* scu = platform_scu();
led_off(0);
led_off(1);
led_off(2);
@@ -1037,35 +814,116 @@ void pin_setup(void)
led_off(3);
#endif
gpio_output(&gpio_led[0]);
gpio_output(&gpio_led[1]);
gpio_output(&gpio_led[2]);
gpio_output(gpio->led[0]);
gpio_output(gpio->led[1]);
gpio_output(gpio->led[2]);
#if (defined RAD1O || defined PRALINE)
gpio_output(&gpio_led[3]);
gpio_output(gpio->led[3]);
#endif
/* Configure drivers and driver pins */
ssp_config_max283x.gpio_select = gpio->max283x_select;
#if defined(PRALINE)
ssp_config_max283x.data_bits = SSP_DATA_9BITS; // send 2 words
#else
ssp_config_max283x.data_bits = SSP_DATA_16BITS;
#endif
ssp_config_max5864.gpio_select = gpio->max5864_select;
ssp_config_w25q80bv.gpio_select = gpio->w25q80bv_select;
spi_flash.gpio_hold = gpio->w25q80bv_hold;
spi_flash.gpio_wp = gpio->w25q80bv_wp;
sgpio_config.gpio_q_invert = gpio->q_invert;
#if !defined(PRALINE)
sgpio_config.gpio_trigger_enable = gpio->trigger_enable;
#endif
#if defined(PRALINE)
ssp_config_ice40_fpga.gpio_select = gpio->fpga_cfg_spi_cs;
ice40.gpio_select = gpio->fpga_cfg_spi_cs;
ice40.gpio_creset = gpio->fpga_cfg_creset;
ice40.gpio_cdone = gpio->fpga_cfg_cdone;
#endif
jtag_gpio_cpld.gpio_tck = gpio->cpld_tck;
#if !defined(PRALINE)
jtag_gpio_cpld.gpio_tms = gpio->cpld_tms;
jtag_gpio_cpld.gpio_tdi = gpio->cpld_tdi;
jtag_gpio_cpld.gpio_tdo = gpio->cpld_tdo;
#endif
#if defined(HACKRF_ONE) || defined(PRALINE)
jtag_gpio_cpld.gpio_pp_tms = gpio->cpld_pp_tms;
jtag_gpio_cpld.gpio_pp_tdo = gpio->cpld_pp_tdo;
#endif
ssp1_set_mode_max283x();
mixer_bus_setup(&mixer);
#ifdef HACKRF_ONE
#if defined(HACKRF_ONE)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
rf_path.gpio_rx = &gpio_h1r9_rx;
sgpio_config.gpio_trigger_enable = &gpio_h1r9_trigger_enable;
rf_path.gpio_rx = gpio->h1r9_rx;
sgpio_config.gpio_trigger_enable = gpio->h1r9_trigger_enable;
}
#endif
#ifdef PRALINE
/* Configure RF path */
#if defined(HACKRF_ONE)
rf_path = (rf_path_t){
.switchctrl = 0,
.gpio_hp = gpio->hp,
.gpio_lp = gpio->lp,
.gpio_tx_mix_bp = gpio->tx_mix_bp,
.gpio_no_mix_bypass = gpio->no_mix_bypass,
.gpio_rx_mix_bp = gpio->rx_mix_bp,
.gpio_tx_amp = gpio->tx_amp,
.gpio_tx = gpio->tx,
.gpio_mix_bypass = gpio->mix_bypass,
.gpio_rx = gpio->rx,
.gpio_no_tx_amp_pwr = gpio->no_tx_amp_pwr,
.gpio_amp_bypass = gpio->amp_bypass,
.gpio_rx_amp = gpio->rx_amp,
.gpio_no_rx_amp_pwr = gpio->no_rx_amp_pwr,
};
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
rf_path.gpio_rx = gpio->h1r9_rx;
rf_path.gpio_h1r9_no_ant_pwr = gpio->h1r9_no_ant_pwr;
}
#elif defined(RAD1O)
rf_path = (rf_path_t){
.switchctrl = 0,
.gpio_tx_rx_n = gpio->tx_rx_n,
.gpio_tx_rx = gpio->tx_rx,
.gpio_by_mix = gpio->by_mix,
.gpio_by_mix_n = gpio->by_mix_n,
.gpio_by_amp = gpio->by_amp,
.gpio_by_amp_n = gpio->by_amp_n,
.gpio_mixer_en = gpio->mixer_en,
.gpio_low_high_filt = gpio->low_high_filt,
.gpio_low_high_filt_n = gpio->low_high_filt_n,
.gpio_tx_amp = gpio->tx_amp,
.gpio_rx_lna = gpio->rx_lna,
};
#elif defined(PRALINE)
rf_path = (rf_path_t){
.switchctrl = 0,
.gpio_tx_en = gpio->tx_en,
.gpio_mix_en_n = gpio->mix_en_n,
.gpio_lpf_en = gpio->lpf_en,
.gpio_rf_amp_en = gpio->rf_amp_en,
.gpio_ant_bias_en_n = gpio->ant_bias_en_n,
};
board_rev_t rev = detected_revision();
if ((rev == BOARD_REV_PRALINE_R1_0) || (rev == BOARD_REV_GSG_PRALINE_R1_0)) {
rf_path.gpio_mix_en_n = &gpio_mix_en_n_r1_0;
rf_path.gpio_mix_en_n = gpio->mix_en_n_r1_0;
}
#endif
rf_path_pin_setup(&rf_path);
/* Configure external clock in */
scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
scu_pinmux(scu->PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
sgpio_configure_pin_functions(&sgpio_config);
}
@@ -1073,32 +931,32 @@ void pin_setup(void)
#ifdef PRALINE
void enable_1v2_power(void)
{
gpio_set(&gpio_1v2_enable);
gpio_set(platform_gpio()->gpio_1v2_enable);
}
void disable_1v2_power(void)
{
gpio_clear(&gpio_1v2_enable);
gpio_clear(platform_gpio()->gpio_1v2_enable);
}
void enable_3v3aux_power(void)
{
gpio_clear(&gpio_3v3aux_enable_n);
gpio_clear(platform_gpio()->gpio_3v3aux_enable_n);
}
void disable_3v3aux_power(void)
{
gpio_set(&gpio_3v3aux_enable_n);
gpio_set(platform_gpio()->gpio_3v3aux_enable_n);
}
#else
void enable_1v8_power(void)
{
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
#ifdef HACKRF_ONE
gpio_set(&gpio_h1r9_1v8_enable);
gpio_set(platform_gpio()->h1r9_1v8_enable);
#endif
} else {
gpio_set(&gpio_1v8_enable);
gpio_set(platform_gpio()->gpio_1v8_enable);
}
}
@@ -1106,10 +964,10 @@ void disable_1v8_power(void)
{
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
#ifdef HACKRF_ONE
gpio_clear(&gpio_h1r9_1v8_enable);
gpio_clear(platform_gpio()->h1r9_1v8_enable);
#endif
} else {
gpio_clear(&gpio_1v8_enable);
gpio_clear(platform_gpio()->gpio_1v8_enable);
}
}
#endif
@@ -1117,16 +975,17 @@ void disable_1v8_power(void)
#ifdef HACKRF_ONE
void enable_rf_power(void)
{
const platform_gpio_t* gpio = platform_gpio();
uint32_t i;
/* many short pulses to avoid one big voltage glitch */
for (i = 0; i < 1000; i++) {
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
gpio_set(&gpio_h1r9_vaa_disable);
gpio_clear(&gpio_h1r9_vaa_disable);
gpio_set(gpio->h1r9_vaa_disable);
gpio_clear(gpio->h1r9_vaa_disable);
} else {
gpio_set(&gpio_vaa_disable);
gpio_clear(&gpio_vaa_disable);
gpio_set(gpio->vaa_disable);
gpio_clear(gpio->vaa_disable);
}
}
}
@@ -1134,9 +993,9 @@ void enable_rf_power(void)
void disable_rf_power(void)
{
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
gpio_set(&gpio_h1r9_vaa_disable);
gpio_set(platform_gpio()->h1r9_vaa_disable);
} else {
gpio_set(&gpio_vaa_disable);
gpio_set(platform_gpio()->vaa_disable);
}
}
#endif
@@ -1144,7 +1003,7 @@ void disable_rf_power(void)
#ifdef PRALINE
void enable_rf_power(void)
{
gpio_clear(&gpio_vaa_disable);
gpio_clear(platform_gpio()->vaa_disable);
/* Let the voltage stabilize */
delay(1000000);
@@ -1152,14 +1011,14 @@ void enable_rf_power(void)
void disable_rf_power(void)
{
gpio_set(&gpio_vaa_disable);
gpio_set(platform_gpio()->vaa_disable);
}
#endif
#ifdef RAD1O
void enable_rf_power(void)
{
gpio_set(&gpio_vaa_enable);
gpio_set(platform_gpio()->vaa_enable);
/* Let the voltage stabilize */
delay(1000000);
@@ -1167,35 +1026,35 @@ void enable_rf_power(void)
void disable_rf_power(void)
{
gpio_clear(&gpio_vaa_enable);
gpio_clear(platform_gpio()->vaa_enable);
}
#endif
#ifdef PRALINE
void led_on(const led_t led)
{
gpio_clear(&gpio_led[led]);
gpio_clear(platform_gpio()->led[led]);
}
void led_off(const led_t led)
{
gpio_set(&gpio_led[led]);
gpio_set(platform_gpio()->led[led]);
}
#else
void led_on(const led_t led)
{
gpio_set(&gpio_led[led]);
gpio_set(platform_gpio()->led[led]);
}
void led_off(const led_t led)
{
gpio_clear(&gpio_led[led]);
gpio_clear(platform_gpio()->led[led]);
}
#endif
void led_toggle(const led_t led)
{
gpio_toggle(&gpio_led[led]);
gpio_toggle(platform_gpio()->led[led]);
}
void set_leds(const uint8_t state)
@@ -1206,9 +1065,9 @@ void set_leds(const uint8_t state)
#endif
for (int i = 0; i < num_leds; i++) {
#ifdef PRALINE
gpio_write(&gpio_led[i], ((state >> i) & 1) == 0);
gpio_write(platform_gpio()->led[i], ((state >> i) & 1) == 0);
#else
gpio_write(&gpio_led[i], ((state >> i) & 1) == 1);
gpio_write(platform_gpio()->led[i], ((state >> i) & 1) == 1);
#endif
}
}
@@ -1240,29 +1099,33 @@ void halt_and_flash(const uint32_t duration)
#ifdef PRALINE
void p1_ctrl_set(const p1_ctrl_signal_t signal)
{
gpio_write(&gpio_p1_ctrl0, signal & 1);
gpio_write(&gpio_p1_ctrl1, (signal >> 1) & 1);
gpio_write(&gpio_p1_ctrl2, (signal >> 2) & 1);
const platform_gpio_t* gpio = platform_gpio();
gpio_write(gpio->p1_ctrl0, signal & 1);
gpio_write(gpio->p1_ctrl1, (signal >> 1) & 1);
gpio_write(gpio->p1_ctrl2, (signal >> 2) & 1);
}
void p2_ctrl_set(const p2_ctrl_signal_t signal)
{
gpio_write(&gpio_p2_ctrl0, signal & 1);
gpio_write(&gpio_p2_ctrl1, (signal >> 1) & 1);
const platform_gpio_t* gpio = platform_gpio();
gpio_write(gpio->p2_ctrl0, signal & 1);
gpio_write(gpio->p2_ctrl1, (signal >> 1) & 1);
}
void clkin_ctrl_set(const clkin_signal_t signal)
{
gpio_write(&gpio_clkin_ctrl, signal & 1);
gpio_write(platform_gpio()->clkin_ctrl, signal & 1);
}
void pps_out_set(const uint8_t value)
{
gpio_write(&gpio_pps_out, value & 1);
gpio_write(platform_gpio()->pps_out, value & 1);
}
void narrowband_filter_set(const uint8_t value)
{
gpio_write(&gpio_aa_en, value & 1);
gpio_write(platform_gpio()->aa_en, value & 1);
}
#endif

347
firmware/common/hackrf_core.h
View File

@@ -46,354 +46,11 @@ extern "C" {
#include "fpga.h"
#include "fixed_point.h"
/*
* SCU PinMux
*/
/* GPIO Output PinMux */
#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */
#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
#ifdef RAD1O
#define SCU_PINMUX_LED4 (PB_6) /* GPIO5[26] on PB_6 */
#endif
#ifdef PRALINE
#define SCU_PINMUX_LED4 (P8_6) /* GPIO4[6] on P8_6 */
#endif
#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */
#define SCU_PINMUX_EN1V2 (P8_7) /* GPIO4[7] on P8_7 */
#ifdef PRALINE
#define SCU_PINMUX_EN3V3_AUX_N (P6_7) /* GPIO5[15] on P6_7 */
#define SCU_PINMUX_EN3V3_OC_N (P6_11) /* GPIO3[7] on P6_11 */
#endif
/* GPIO Input PinMux */
#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */
#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */
#ifndef HACKRF_ONE
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
#endif
#define SCU_PINMUX_PP_LCD_TE (P2_3) /* GPIO5[3] on P2_3 */
#define SCU_PINMUX_PP_LCD_RDX (P2_4) /* GPIO5[4] on P2_4 */
#define SCU_PINMUX_PP_UNUSED (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_PP_LCD_WRX (P2_9) /* GPIO1[10] on P2_9 */
#define SCU_PINMUX_PP_DIR (P2_13) /* GPIO1[13] on P2_13 */
/* USB peripheral */
#ifdef JAWBREAKER
#define SCU_PINMUX_USB_LED0 (P6_8)
#define SCU_PINMUX_USB_LED1 (P6_7)
#endif
/* SSP1 Peripheral PinMux */
#define SCU_SSP1_CIPO (P1_3) /* P1_3 */
#define SCU_SSP1_COPI (P1_4) /* P1_4 */
#define SCU_SSP1_SCK (P1_19) /* P1_19 */
#define SCU_SSP1_CS (P1_20) /* P1_20 */
/* CPLD JTAG interface */
#ifdef PRALINE
#define SCU_PINMUX_FPGA_CRESET (P5_2) /* GPIO2[11] on P5_2 */
#define SCU_PINMUX_FPGA_CDONE (P4_10) /* GPIO5[14] */
#define SCU_PINMUX_FPGA_SPI_CS (P5_1) /* GPIO2[10] */
#endif
#define SCU_PINMUX_CPLD_TDO (P9_5) /* GPIO5[18] */
#define SCU_PINMUX_CPLD_TCK (P6_1) /* GPIO3[ 0] */
#if (defined HACKRF_ONE || defined RAD1O || defined PRALINE)
#define SCU_PINMUX_CPLD_TMS (P6_5) /* GPIO3[ 4] */
#define SCU_PINMUX_CPLD_TDI (P6_2) /* GPIO3[ 1] */
#else
#define SCU_PINMUX_CPLD_TMS (P6_2) /* GPIO3[ 1] */
#define SCU_PINMUX_CPLD_TDI (P6_5) /* GPIO3[ 4] */
#endif
/* CPLD SGPIO interface */
#ifdef PRALINE
#define SCU_PINMUX_SGPIO0 (P0_0)
#define SCU_PINMUX_SGPIO1 (P0_1)
#define SCU_PINMUX_SGPIO2 (P1_15)
#define SCU_PINMUX_SGPIO3 (P1_16)
#define SCU_PINMUX_SGPIO4 (P9_4)
#define SCU_PINMUX_SGPIO5 (P6_6)
#define SCU_PINMUX_SGPIO6 (P2_2)
#define SCU_PINMUX_SGPIO7 (P1_0)
#define SCU_PINMUX_SGPIO8 (P8_0)
#define SCU_PINMUX_SGPIO9 (P9_3)
#define SCU_PINMUX_SGPIO10 (P8_2)
#define SCU_PINMUX_SGPIO11 (P1_17)
#define SCU_PINMUX_SGPIO12 (P1_18)
#define SCU_PINMUX_SGPIO14 (P1_18)
#define SCU_PINMUX_SGPIO15 (P1_18)
#define SCU_PINMUX_SGPIO0_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
#define SCU_PINMUX_SGPIO1_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
#define SCU_PINMUX_SGPIO2_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO3_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO4_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO5_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO6_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_PINMUX_SGPIO7_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO8_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_PINMUX_SGPIO9_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO10_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_PINMUX_SGPIO11_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO12_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_PINMUX_SGPIO14_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_PINMUX_SGPIO15_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#else
#define SCU_PINMUX_SGPIO0 (P0_0)
#define SCU_PINMUX_SGPIO1 (P0_1)
#define SCU_PINMUX_SGPIO2 (P1_15)
#define SCU_PINMUX_SGPIO3 (P1_16)
#define SCU_PINMUX_SGPIO4 (P6_3)
#define SCU_PINMUX_SGPIO5 (P6_6)
#define SCU_PINMUX_SGPIO6 (P2_2)
#define SCU_PINMUX_SGPIO7 (P1_0)
#if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O)
#define SCU_PINMUX_SGPIO8 (P9_6)
#endif
#define SCU_PINMUX_SGPIO9 (P4_3)
#define SCU_PINMUX_SGPIO10 (P1_14)
#define SCU_PINMUX_SGPIO11 (P1_17)
#define SCU_PINMUX_SGPIO12 (P1_18)
#define SCU_PINMUX_SGPIO14 (P4_9)
#define SCU_PINMUX_SGPIO15 (P4_10)
#define SCU_PINMUX_SGPIO0_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
#define SCU_PINMUX_SGPIO1_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
#define SCU_PINMUX_SGPIO2_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO3_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO4_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO5_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
#define SCU_PINMUX_SGPIO6_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_PINMUX_SGPIO7_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO8_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO9_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION7)
#define SCU_PINMUX_SGPIO10_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO11_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
#define SCU_PINMUX_SGPIO12_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_PINMUX_SGPIO14_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_PINMUX_SGPIO15_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#endif
#define SCU_TRIGGER_EN (P4_8) /* GPIO5[12] on P4_8 */
/* MAX2837 GPIO (XCVR_CTL) PinMux */
#ifdef RAD1O
#define SCU_XCVR_RXHP (P8_1) /* GPIO[] on P8_1 */
#define SCU_XCVR_B6 (P8_2) /* GPIO[] on P8_2 */
#define SCU_XCVR_B7 (P9_3) /* GPIO[] on P8_3 */
#endif
#ifdef PRALINE
#define SCU_XCVR_ENABLE (PE_1) /* GPIO7[1] on PE_1 */
#define SCU_XCVR_RXENABLE (PE_2) /* GPIO7[2] on PE_2 */
#define SCU_XCVR_CS (PD_14) /* GPIO6[28] on PD_14 */
#define SCU_XCVR_RXHP (PD_15) /* GPIO6[29] on PD_15 */
#define SCU_XCVR_LD (P9_6) /* GPIO4[11] on P9_6 */
#define SCU_XCVR_ENABLE_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_XCVR_RXENABLE_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_XCVR_CS_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_XCVR_RXHP_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_XCVR_LD_PINCFG \
(SCU_GPIO_FAST | SCU_CONF_FUNCTION0 | SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EPUN_DIS_PULLUP)
#else
#define SCU_XCVR_ENABLE (P4_6) /* GPIO2[6] on P4_6 */
#define SCU_XCVR_RXENABLE (P4_5) /* GPIO2[5] on P4_5 */
#define SCU_XCVR_TXENABLE (P4_4) /* GPIO2[4] on P4_4 */
#define SCU_XCVR_CS (P1_20) /* GPIO0[15] on P1_20 */
#define SCU_XCVR_ENABLE_PINCFG (SCU_GPIO_FAST)
#define SCU_XCVR_RXENABLE_PINCFG (SCU_GPIO_FAST)
#define SCU_XCVR_TXENABLE_PINCFG (SCU_GPIO_FAST)
#define SCU_XCVR_CS_PINCFG (SCU_GPIO_FAST)
#endif
/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
#ifdef PRALINE
#define SCU_AD_CS (PD_16) /* GPIO6[30] on PD_16 */
#define SCU_AD_CS_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#else
#define SCU_AD_CS (P5_7) /* GPIO2[7] on P5_7 */
#define SCU_AD_CS_PINCFG (SCU_GPIO_FAST)
#endif
/* RFFC5071 GPIO serial interface PinMux */
#if (defined JAWBREAKER || defined HACKRF_ONE)
#define SCU_MIXER_ENX (P5_4) /* GPIO2[13] on P5_4 */
#define SCU_MIXER_SCLK (P2_6) /* GPIO5[6] on P2_6 */
#define SCU_MIXER_SDATA (P6_4) /* GPIO3[3] on P6_4 */
#define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */
#define SCU_MIXER_SCLK_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_MIXER_SDATA_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#endif
#ifdef PRALINE
#define SCU_MIXER_ENX (P5_4) /* GPIO2[13] on P5_4 */
#define SCU_MIXER_SCLK (P9_5) /* GPIO5[18] on P9_5 */
#define SCU_MIXER_SDATA (P9_2) /* GPIO4[14] on P9_2 */
#define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */
#define SCU_MIXER_LD (PD_11) /* GPIO6[25] on PD_11 */
#define SCU_MIXER_SCLK_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_MIXER_SDATA_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_MIXER_LD_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#endif
#ifdef RAD1O
#define SCU_VCO_CE (P5_4) /* GPIO2[13] on P5_4 */
#define SCU_VCO_SCLK (P2_6) /* GPIO5[6] on P2_6 */
#define SCU_VCO_SDATA (P6_4) /* GPIO3[3] on P6_4 */
#define SCU_VCO_LE (P5_5) /* GPIO2[14] on P5_5 */
#define SCU_VCO_MUX (PB_5) /* GPIO5[25] on PB_5 */
#define SCU_MIXER_EN (P6_8) /* GPIO5[16] on P6_8 */
#define SCU_SYNT_RFOUT_EN (P6_9) /* GPIO3[5] on P6_9 */
#endif
/* RF LDO control */
#ifdef JAWBREAKER
#define SCU_RF_LDO_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
#endif
/* RF supply (VAA) control */
#ifdef HACKRF_ONE
#define SCU_NO_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
#endif
#ifdef PRALINE
#define SCU_NO_VAA_ENABLE (P8_1) /* GPIO4[1] on P8_1 */
#endif
#ifdef RAD1O
#define SCU_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
#endif
/* SPI flash */
#define SCU_SSP0_CIPO (P3_6)
#define SCU_SSP0_COPI (P3_7)
#define SCU_SSP0_SCK (P3_3)
#define SCU_SSP0_CS (P3_8) /* GPIO5[11] on P3_8 */
#define SCU_FLASH_HOLD (P3_4) /* GPIO1[14] on P3_4 */
#define SCU_FLASH_WP (P3_5) /* GPIO1[15] on P3_5 */
/* RF switch control */
#ifdef HACKRF_ONE
#define SCU_HP (P4_0) /* GPIO2[0] on P4_0 */
#define SCU_LP (P5_1) /* GPIO2[10] on P5_1 */
#define SCU_TX_MIX_BP (P5_2) /* GPIO2[11] on P5_2 */
#define SCU_NO_MIX_BYPASS (P1_7) /* GPIO1[0] on P1_7 */
#define SCU_RX_MIX_BP (P5_3) /* GPIO2[12] on P5_3 */
#define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */
#define SCU_TX (P6_7) /* GPIO5[15] on P6_7 */
#define SCU_MIX_BYPASS (P6_8) /* GPIO5[16] on P6_8 */
#define SCU_RX (P2_5) /* GPIO5[5] on P2_5 */
#define SCU_NO_TX_AMP_PWR (P6_9) /* GPIO3[5] on P6_9 */
#define SCU_AMP_BYPASS (P2_10) /* GPIO0[14] on P2_10 */
#define SCU_RX_AMP (P2_11) /* GPIO1[11] on P2_11 */
#define SCU_NO_RX_AMP_PWR (P2_12) /* GPIO1[12] on P2_12 */
#endif
#ifdef RAD1O
#define SCU_BY_AMP (P1_7) /* GPIO1[0] on P1_7 */
#define SCU_BY_AMP_N (P2_5) /* GPIO5[5] on P2_5 */
#define SCU_TX_RX (P2_10) /* GPIO0[14] on P2_10 */
#define SCU_TX_RX_N (P2_11) /* GPIO1[11] on P2_11 */
#define SCU_BY_MIX (P2_12) /* GPIO1[12] on P2_12 */
#define SCU_BY_MIX_N (P5_1) /* GPIO2[10] on P5_1 */
#define SCU_LOW_HIGH_FILT (P5_2) /* GPIO2[11] on P5_2 */
#define SCU_LOW_HIGH_FILT_N (P5_3) /* GPIO2[12] on P5_3 */
#define SCU_TX_AMP (P5_6) /* GPIO2[15] on P5_6 */
#define SCU_RX_LNA (P6_7) /* GPIO5[15] on P6_7 */
#endif
#ifdef PRALINE
#define SCU_TX_EN (P6_5) /* GPIO3[4] on P6_5 */
#define SCU_MIX_EN_N (P6_3) /* GPIO3[2] on P6_3 */
#define SCU_MIX_EN_N_R1_0 (P2_6) /* GPIO5[6] on P2_6 */
#define SCU_LPF_EN (PA_1) /* GPIO4[8] on PA_1 */
#define SCU_RF_AMP_EN (PA_2) /* GPIO4[9] on PA_2 */
#define SCU_ANT_BIAS_EN_N (P2_12) /* GPIO1[12] on P2_12 */
#define SCU_ANT_BIAS_OC_N (P2_11) /* GPIO1[11] on P2_11 */
#endif
#ifdef PRALINE
#define SCU_P2_CTRL0 (PE_3) /* GPIO7[3] on PE_3 */
#define SCU_P2_CTRL1 (PE_4) /* GPIO7[4] on PE_4 */
#define SCU_P1_CTRL0 (P2_10) /* GPIO0[14] on P2_10 */
#define SCU_P1_CTRL1 (P6_8) /* GPIO5[16] on P6_8 */
#define SCU_P1_CTRL2 (P6_9) /* GPIO3[5] on P6_9 */
#define SCU_CLKIN_CTRL (P1_20) /* GPIO0[15] on P1_20 */
#define SCU_AA_EN (P1_14) /* GPIO1[7] on P1_14 */
#define SCU_TRIGGER_IN (PD_12) /* GPIO6[26] on PD_12 */
#define SCU_TRIGGER_OUT (P2_6) /* GPIO5[6] on P2_6 */
#define SCU_PPS_OUT (P2_5) /* GPIO5[5] on P2_5 */
#define SCU_P2_CTRL0_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_P2_CTRL1_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_P1_CTRL0_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_P1_CTRL1_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_P1_CTRL2_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_CLKIN_CTRL_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_AA_EN_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
#define SCU_TRIGGER_IN_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_TRIGGER_OUT_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#define SCU_PPS_OUT_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
#endif
#define SCU_PINMUX_PP_D0 (P7_0) /* GPIO3[8] */
#define SCU_PINMUX_PP_D1 (P7_1) /* GPIO3[9] */
#define SCU_PINMUX_PP_D2 (P7_2) /* GPIO3[10] */
#define SCU_PINMUX_PP_D3 (P7_3) /* GPIO3[11] */
#define SCU_PINMUX_PP_D4 (P7_4) /* GPIO3[12] */
#define SCU_PINMUX_PP_D5 (P7_5) /* GPIO3[13] */
#define SCU_PINMUX_PP_D6 (P7_6) /* GPIO3[14] */
#define SCU_PINMUX_PP_D7 (P7_7) /* GPIO3[15] */
/* TODO add other Pins */
#define SCU_PINMUX_GPIO3_8 (P7_0) /* GPIO3[8] */
#define SCU_PINMUX_GPIO3_9 (P7_1) /* GPIO3[9] */
#define SCU_PINMUX_GPIO3_10 (P7_2) /* GPIO3[10] */
#define SCU_PINMUX_GPIO3_11 (P7_3) /* GPIO3[11] */
#define SCU_PINMUX_GPIO3_12 (P7_4) /* GPIO3[12] */
#define SCU_PINMUX_GPIO3_13 (P7_5) /* GPIO3[13] */
#define SCU_PINMUX_GPIO3_14 (P7_6) /* GPIO3[14] */
#define SCU_PINMUX_GPIO3_15 (P7_7) /* GPIO3[15] */
#define SCU_PINMUX_PP_TDO (P1_5) /* GPIO1[8] */
#define SCU_PINMUX_SD_POW (P1_5) /* GPIO1[8] */
#define SCU_PINMUX_SD_CMD (P1_6) /* GPIO1[9] */
#define SCU_PINMUX_PP_TMS (P1_8) /* GPIO1[1] */
#define SCU_PINMUX_SD_VOLT0 (P1_8) /* GPIO1[1] */
#define SCU_PINMUX_SD_DAT0 (P1_9) /* GPIO1[2] */
#define SCU_PINMUX_SD_DAT1 (P1_10) /* GPIO1[3] */
#define SCU_PINMUX_SD_DAT2 (P1_11) /* GPIO1[4] */
#define SCU_PINMUX_SD_DAT3 (P1_12) /* GPIO1[5] */
#define SCU_PINMUX_SD_CD (P1_13) /* GPIO1[6] */
#define SCU_PINMUX_PP_IO_STBX (P2_0) /* GPIO5[0] */
#define SCU_PINMUX_PP_ADDR (P2_1) /* GPIO5[1] */
#define SCU_PINMUX_U0_TXD (P2_0) /* GPIO5[0] */
#define SCU_PINMUX_U0_RXD (P2_1) /* GPIO5[1] */
#define SCU_PINMUX_ISP (P2_7) /* GPIO0[7] */
#define SCU_PINMUX_GP_CLKIN (P4_7)
/* HackRF One r9 */
#define SCU_H1R9_CLKIN_EN (P6_7) /* GPIO5[15] on P6_7 */
#define SCU_H1R9_CLKOUT_EN (P1_2) /* GPIO0[9] on P1_2 (has boot pull-down) */
#define SCU_H1R9_MCU_CLK_EN (P1_1) /* GPIO0[8] on P1_1 (has boot pull-up) */
#define SCU_H1R9_RX (P2_7) /* GPIO0[7] on P4_4 (has boot pull-up) */
#define SCU_H1R9_NO_ANT_PWR (P4_4) /* GPIO2[4] on P4_4 */
#define SCU_H1R9_EN1V8 (P5_0) /* GPIO2[9] on P5_0 */
#define SCU_H1R9_NO_VAA_EN (P6_10) /* GPIO3[6] on P6_10 */
#define SCU_H1R9_TRIGGER_EN (P2_5) /* GPIO5[5] on P2_5 */
#include "platform_scu.h"
/* TODO: Hide these configurations */
extern si5351c_driver_t clock_gen;
extern const ssp_config_t ssp_config_w25q80bv;
extern const ssp_config_t ssp_config_max283x;
extern const ssp_config_t ssp_config_max5864;
extern ssp_config_t ssp_config_w25q80bv;
#ifdef PRALINE
extern ice40_spi_driver_t ice40;

16
firmware/common/ice40_spi.c
View File

@@ -21,20 +21,22 @@
#include "ice40_spi.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "lz4_buf.h"
#include "delay.h"
#include "platform_scu.h"
void ice40_spi_target_init(ice40_spi_driver_t* const drv)
{
const platform_scu_t* scu = platform_scu();
/* Configure SSP1 Peripheral and relevant FPGA pins. */
scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(scu->PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
scu_pinmux(scu->PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
/* Configure GPIOs as inputs or outputs as needed. */
gpio_clear(drv->gpio_creset);

21
firmware/common/max2831_target.c
View File

@@ -21,16 +21,17 @@
#include "max2831_target.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
void max2831_target_init(max2831_driver_t* const drv)
{
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
const platform_scu_t* scu = platform_scu();
scu_pinmux(SCU_XCVR_CS, SCU_XCVR_CS_PINCFG);
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(scu->XCVR_CS, scu->XCVR_CS_PINCFG);
/*
* Configure XCVR_CTL GPIO pins.
@@ -39,10 +40,10 @@ void max2831_target_init(max2831_driver_t* const drv)
* MAX2837 which had a separate TXENABLE. On MAX2831 a single RXTX pin
* switches between RX (high) and TX (low) modes.
*/
scu_pinmux(SCU_XCVR_ENABLE, SCU_XCVR_ENABLE_PINCFG);
scu_pinmux(SCU_XCVR_RXENABLE, SCU_XCVR_RXENABLE_PINCFG);
scu_pinmux(SCU_XCVR_RXHP, SCU_XCVR_RXHP_PINCFG);
scu_pinmux(SCU_XCVR_LD, SCU_XCVR_LD_PINCFG);
scu_pinmux(scu->XCVR_ENABLE, scu->XCVR_ENABLE_PINCFG);
scu_pinmux(scu->XCVR_RXENABLE, scu->XCVR_RXENABLE_PINCFG);
scu_pinmux(scu->XCVR_RXHP, scu->XCVR_RXHP_PINCFG);
scu_pinmux(scu->XCVR_LD, scu->XCVR_LD_PINCFG);
/* Set GPIO pins as outputs. */
gpio_output(drv->gpio_enable);

21
firmware/common/max2837_target.c
View File

@@ -23,22 +23,23 @@
#include "max2837_target.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
void max2837_target_init(max2837_driver_t* const drv)
{
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
const platform_scu_t* scu = platform_scu();
scu_pinmux(SCU_XCVR_CS, SCU_XCVR_CS_PINCFG);
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(scu->XCVR_CS, scu->XCVR_CS_PINCFG);
/* Configure XCVR_CTL GPIO pins. */
scu_pinmux(SCU_XCVR_ENABLE, SCU_XCVR_ENABLE_PINCFG);
scu_pinmux(SCU_XCVR_RXENABLE, SCU_XCVR_RXENABLE_PINCFG);
scu_pinmux(SCU_XCVR_TXENABLE, SCU_XCVR_TXENABLE_PINCFG);
scu_pinmux(scu->XCVR_ENABLE, scu->XCVR_ENABLE_PINCFG);
scu_pinmux(scu->XCVR_RXENABLE, scu->XCVR_RXENABLE_PINCFG);
scu_pinmux(scu->XCVR_TXENABLE, scu->XCVR_TXENABLE_PINCFG);
/* Set GPIO pins as outputs. */
gpio_output(drv->gpio_enable);

19
firmware/common/max2839_target.c
View File

@@ -23,17 +23,18 @@
#include "max2839_target.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
void max2839_target_init(max2839_driver_t* const drv)
{
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
const platform_scu_t* scu = platform_scu();
scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(scu->XCVR_CS, SCU_GPIO_FAST);
/*
* Configure XCVR_CTL GPIO pins.
@@ -42,8 +43,8 @@ void max2839_target_init(max2839_driver_t* const drv)
* MAX2837 which had a separate TXENABLE. On MAX2839 a single RXTX pin
* switches between RX (high) and TX (low) modes.
*/
scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);
scu_pinmux(scu->XCVR_ENABLE, SCU_GPIO_FAST);
scu_pinmux(scu->XCVR_RXENABLE, SCU_GPIO_FAST);
/* Set GPIO pins as outputs. */
gpio_output(drv->gpio_enable);

39
firmware/common/max283x.c
View File

@@ -23,46 +23,26 @@
#include "max283x.h"
#include "gpio.h"
#include "gpio_lpc.h"
#include "platform_gpio.h"
#include "spi_bus.h"
extern spi_bus_t spi_bus_ssp1;
#ifdef PRALINE
static struct gpio gpio_max283x_enable = GPIO(7, 1);
static struct gpio gpio_max283x_rx_enable = GPIO(7, 2);
static struct gpio gpio_max2831_rxhp = GPIO(6, 29);
static struct gpio gpio_max2831_ld = GPIO(4, 11);
#else
static struct gpio gpio_max283x_enable = GPIO(2, 6);
static struct gpio gpio_max283x_rx_enable = GPIO(2, 5);
static struct gpio gpio_max283x_tx_enable = GPIO(2, 4);
#endif
#ifdef PRALINE
max2831_driver_t max2831 = {
.bus = &spi_bus_ssp1,
.gpio_enable = &gpio_max283x_enable,
.gpio_rxtx = &gpio_max283x_rx_enable,
.gpio_rxhp = &gpio_max2831_rxhp,
.gpio_ld = &gpio_max2831_ld,
.target_init = max2831_target_init,
.set_mode = max2831_target_set_mode,
};
#else
max2837_driver_t max2837 = {
.bus = &spi_bus_ssp1,
.gpio_enable = &gpio_max283x_enable,
.gpio_rx_enable = &gpio_max283x_rx_enable,
.gpio_tx_enable = &gpio_max283x_tx_enable,
.target_init = max2837_target_init,
.set_mode = max2837_target_set_mode,
};
max2839_driver_t max2839 = {
.bus = &spi_bus_ssp1,
.gpio_enable = &gpio_max283x_enable,
.gpio_rxtx = &gpio_max283x_rx_enable,
.target_init = max2839_target_init,
.set_mode = max2839_target_set_mode,
};
@@ -72,6 +52,23 @@ max2839_driver_t max2839 = {
void max283x_setup(max283x_driver_t* const drv, max283x_variant_t type)
{
drv->type = type;
const platform_gpio_t* gpio = platform_gpio();
/* MAX283x GPIO PinMux */
#if defined(PRALINE)
max2831.gpio_enable = gpio->max283x_enable;
max2831.gpio_rxtx = gpio->max283x_rx_enable;
max2831.gpio_rxhp = gpio->max2831_rxhp;
max2831.gpio_ld = gpio->max2831_ld;
#else
max2837.gpio_enable = gpio->max283x_enable;
max2837.gpio_rx_enable = gpio->max283x_rx_enable;
max2837.gpio_tx_enable = gpio->max283x_tx_enable;
max2839.gpio_enable = gpio->max283x_enable;
max2839.gpio_rxtx = gpio->max283x_rx_enable;
#endif
switch (type) {
#ifdef PRALINE
case MAX2831_VARIANT:

16
firmware/common/max2871.c
View File

@@ -43,14 +43,16 @@ static void delay_ms(int ms);
void max2871_setup(max2871_driver_t* const drv)
{
const platform_scu_t* scu = platform_scu();
/* Configure GPIO pins. */
scu_pinmux(SCU_VCO_CE, SCU_GPIO_FAST);
scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
/* Only used for the debug pin config: scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST); */
scu_pinmux(SCU_VCO_SDATA, SCU_GPIO_FAST);
scu_pinmux(SCU_VCO_LE, SCU_GPIO_FAST);
scu_pinmux(SCU_VCO_MUX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_SYNT_RFOUT_EN, SCU_GPIO_FAST);
scu_pinmux(scu->VCO_CE, SCU_GPIO_FAST);
scu_pinmux(scu->VCO_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
/* Only used for the debug pin config: scu_pinmux(scu->VCO_SCLK, SCU_GPIO_FAST); */
scu_pinmux(scu->VCO_SDATA, SCU_GPIO_FAST);
scu_pinmux(scu->VCO_LE, SCU_GPIO_FAST);
scu_pinmux(scu->VCO_MUX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->SYNT_RFOUT_EN, SCU_GPIO_FAST);
/* Set GPIO pins as outputs. */
gpio_output(drv->gpio_vco_ce);

13
firmware/common/max5864_target.c
View File

@@ -22,21 +22,22 @@
#include "max5864_target.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
void max5864_target_init(max5864_driver_t* const drv)
{
(void) drv;
const platform_scu_t* scu = platform_scu();
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/*
* Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
* SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
*/
scu_pinmux(SCU_AD_CS, SCU_AD_CS_PINCFG);
scu_pinmux(scu->AD_CS, scu->AD_CS_PINCFG);
}

100
firmware/common/mixer.c
View File

@@ -23,39 +23,10 @@
#include "rffc5071.h"
#include "rffc5071_spi.h"
#include "max2871.h"
#include "gpio_lpc.h"
#include "platform_gpio.h"
/* RFFC5071 GPIO serial interface PinMux */
// clang-format off
#if (defined JAWBREAKER || defined HACKRF_ONE)
static struct gpio gpio_rffc5072_select = GPIO(2, 13);
static struct gpio gpio_rffc5072_clock = GPIO(5, 6);
static struct gpio gpio_rffc5072_data = GPIO(3, 3);
static struct gpio gpio_rffc5072_reset = GPIO(2, 14);
#endif
#ifdef RAD1O
static struct gpio gpio_vco_ce = GPIO(2, 13);
static struct gpio gpio_vco_sclk = GPIO(5, 6);
static struct gpio gpio_vco_sdata = GPIO(3, 3);
static struct gpio gpio_vco_le = GPIO(2, 14);
static struct gpio gpio_vco_mux = GPIO(5, 25);
static struct gpio gpio_synt_rfout_en = GPIO(3, 5);
#endif
#ifdef PRALINE
static struct gpio gpio_rffc5072_select = GPIO(2, 13);
static struct gpio gpio_rffc5072_clock = GPIO(5, 18);
static struct gpio gpio_rffc5072_data = GPIO(4, 14);
static struct gpio gpio_rffc5072_reset = GPIO(2, 14);
static struct gpio gpio_rffc5072_ld = GPIO(6, 25);
#endif
// clang-format on
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
const rffc5071_spi_config_t rffc5071_spi_config = {
.gpio_select = &gpio_rffc5072_select,
.gpio_clock = &gpio_rffc5072_clock,
.gpio_data = &gpio_rffc5072_data,
};
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
static rffc5071_spi_config_t rffc5071_spi_config;
spi_bus_t spi_bus_rffc5071 = {
.config = &rffc5071_spi_config,
@@ -67,80 +38,79 @@ spi_bus_t spi_bus_rffc5071 = {
mixer_driver_t mixer = {
.bus = &spi_bus_rffc5071,
.gpio_reset = &gpio_rffc5072_reset,
#ifdef PRALINE
.gpio_ld = &gpio_rffc5072_ld,
#endif
};
#endif
#ifdef RAD1O
mixer_driver_t mixer = {
.gpio_vco_ce = &gpio_vco_ce,
.gpio_vco_sclk = &gpio_vco_sclk,
.gpio_vco_sdata = &gpio_vco_sdata,
.gpio_vco_le = &gpio_vco_le,
.gpio_synt_rfout_en = &gpio_synt_rfout_en,
.gpio_vco_mux = &gpio_vco_mux,
};
#elif defined(RAD1O)
mixer_driver_t mixer = {};
#endif
void mixer_bus_setup(mixer_driver_t* const mixer)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
(void) mixer;
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
const platform_gpio_t* gpio = platform_gpio();
rffc5071_spi_config = (rffc5071_spi_config_t){
.gpio_select = gpio->rffc5072_select,
.gpio_clock = gpio->rffc5072_clock,
.gpio_data = gpio->rffc5072_data,
};
spi_bus_start(&spi_bus_rffc5071, &rffc5071_spi_config);
#endif
#ifdef RAD1O
(void) mixer;
#endif
}
void mixer_setup(mixer_driver_t* const mixer)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
const platform_gpio_t* gpio = platform_gpio();
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
mixer->gpio_reset = gpio->rffc5072_reset;
#if defined(PRALINE)
mixer->gpio_ld = gpio->rffc5072_ld;
#endif
rffc5071_setup(mixer);
#endif
#ifdef RAD1O
#elif defined(RAD1O)
mixer->gpio_vco_ce = gpio->vco_ce;
mixer->gpio_vco_sclk = gpio->vco_sclk;
mixer->gpio_vco_sdata = gpio->vco_sdata;
mixer->gpio_vco_le = gpio->vco_le;
mixer->gpio_synt_rfout_en = gpio->synt_rfout_en;
mixer->gpio_vco_mux = gpio->vco_mux;
max2871_setup(mixer);
#endif
}
uint64_t mixer_set_frequency(mixer_driver_t* const mixer, uint64_t hz)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
return rffc5071_set_frequency(mixer, hz);
#endif
#ifdef RAD1O
#elif defined(RAD1O)
return max2871_set_frequency(mixer, hz / 1000000);
#endif
}
void mixer_enable(mixer_driver_t* const mixer)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
rffc5071_enable(mixer);
#endif
#ifdef RAD1O
#elif defined(RAD1O)
max2871_enable(mixer);
#endif
}
void mixer_disable(mixer_driver_t* const mixer)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
rffc5071_disable(mixer);
#endif
#ifdef RAD1O
#elif defined(RAD1O)
max2871_disable(mixer);
#endif
}
void mixer_set_gpo(mixer_driver_t* const mixer, uint8_t gpo)
{
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
#if defined(JAWBREAKER) || defined(HACKRF_ONE) || defined(PRALINE)
rffc5071_set_gpo(mixer, gpo);
#endif
#ifdef RAD1O
#elif defined(RAD1O)
(void) mixer;
(void) gpo;
#endif

4
firmware/common/mixer.h
View File

@@ -26,9 +26,7 @@
#if (defined JAWBREAKER || defined HACKRF_ONE || defined PRALINE)
#include "rffc5071.h"
typedef rffc5071_driver_t mixer_driver_t;
#endif
#ifdef RAD1O
#elif defined(RAD1O)
#include "max2871.h"
typedef max2871_driver_t mixer_driver_t;
#endif

14
firmware/common/operacake.c
View File

@@ -26,7 +26,7 @@
#include "gpio.h"
#include "gpio_lpc.h"
#include "i2c_bus.h"
#include <libopencm3/lpc43xx/scu.h>
#include "platform_scu.h"
/*
* I2C Mode
@@ -387,11 +387,13 @@ uint16_t gpio_test(uint8_t address)
return 0xFFFF;
}
scu_pinmux(SCU_PINMUX_GPIO3_8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_GPIO3_12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_GPIO3_13, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_GPIO3_14, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_PINMUX_GPIO3_15, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
const platform_scu_t* scu = platform_scu();
scu_pinmux(scu->PINMUX_GPIO3_8, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_12, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_13, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_14, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->PINMUX_GPIO3_15, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
static struct gpio gpio_pins[] = {
GPIO(3, 8), // u1ctrl IO2

4
firmware/common/platform_gpio.h
View File

@@ -31,7 +31,11 @@ extern "C" {
typedef struct {
/* LEDs */
#if defined(PRALINE) || defined(RAD1O)
gpio_t led[4];
#else
gpio_t led[3];
#endif
/* Power Supply Control */
gpio_t gpio_1v8_enable;

62
firmware/common/portapack.c
View File

@@ -23,30 +23,16 @@
#include "portapack.h"
#include "hackrf_core.h"
#include "gpio_lpc.h"
#include "platform_gpio.h"
#include "platform_scu.h"
#include "delay.h"
#include <libopencm3/lpc43xx/scu.h>
static void portapack_sleep_milliseconds(const uint32_t milliseconds)
{
/* NOTE: Naively assumes 204 MHz instruction cycle clock and five instructions per count */
delay(milliseconds * 40800);
}
// clang-format off
static struct gpio gpio_io_stbx = GPIO(5, 0); /* P2_0 */
static struct gpio gpio_addr = GPIO(5, 1); /* P2_1 */
__attribute__((unused))
static struct gpio gpio_lcd_te = GPIO(5, 3); /* P2_3 */
__attribute__((unused))
static struct gpio gpio_unused = GPIO(5, 7); /* P2_8 */
static struct gpio gpio_lcd_rdx = GPIO(5, 4); /* P2_4 */
static struct gpio gpio_lcd_wrx = GPIO(1, 10); /* P2_9 */
static struct gpio gpio_dir = GPIO(1, 13); /* P2_13 */
// clang-format on
typedef struct portapack_if_t {
gpio_t gpio_dir;
gpio_t gpio_lcd_rdx;
@@ -58,11 +44,6 @@ typedef struct portapack_if_t {
} portapack_if_t;
static portapack_if_t portapack_if = {
.gpio_dir = &gpio_dir,
.gpio_lcd_rdx = &gpio_lcd_rdx,
.gpio_lcd_wrx = &gpio_lcd_wrx,
.gpio_io_stbx = &gpio_io_stbx,
.gpio_addr = &gpio_addr,
.gpio_port_data = GPIO_LPC_PORT(3),
.io_reg = 0x03,
};
@@ -191,6 +172,15 @@ static void portapack_io_write(const bool address, const uint_fast16_t value)
static void portapack_if_init(void)
{
const platform_gpio_t* gpio = platform_gpio();
const platform_scu_t* scu = platform_scu();
portapack_if.gpio_dir = gpio->dir;
portapack_if.gpio_lcd_rdx = gpio->lcd_rdx;
portapack_if.gpio_lcd_wrx = gpio->lcd_wrx;
portapack_if.gpio_io_stbx = gpio->io_stbx;
portapack_if.gpio_addr = gpio->addr;
portapack_data_mask_set();
portapack_data_write_high(0);
@@ -208,22 +198,22 @@ static void portapack_if_init(void)
/* gpio_input(portapack_if.gpio_rot_a); */
/* gpio_input(portapack_if.gpio_rot_b); */
scu_pinmux(SCU_PINMUX_PP_D0, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D1, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D2, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D3, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D4, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D5, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D6, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_D7, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D0, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D1, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D2, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D3, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D4, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D5, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D6, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(scu->PINMUX_PP_D7, SCU_CONF_FUNCTION0 | SCU_GPIO_PDN);
scu_pinmux(SCU_PINMUX_PP_DIR, SCU_CONF_FUNCTION0 | SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_PP_LCD_RDX, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_PP_LCD_WRX, SCU_CONF_FUNCTION0 | SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_PP_IO_STBX, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
scu_pinmux(SCU_PINMUX_PP_ADDR, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
/* scu_pinmux(SCU_PINMUX_PP_LCD_TE, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL); */
/* scu_pinmux(SCU_PINMUX_PP_UNUSED, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL); */
scu_pinmux(scu->PINMUX_PP_DIR, SCU_CONF_FUNCTION0 | SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_PP_LCD_RDX, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_PP_LCD_WRX, SCU_CONF_FUNCTION0 | SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_PP_IO_STBX, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
scu_pinmux(scu->PINMUX_PP_ADDR, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL);
/* scu_pinmux(scu->PINMUX_PP_LCD_TE, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL); */
/* scu_pinmux(scu->PINMUX_PP_UNUSED, SCU_CONF_FUNCTION4 | SCU_GPIO_NOPULL); */
}
static void portapack_lcd_reset_state(const bool active)

92
firmware/common/rf_path.c
View File

@@ -23,13 +23,12 @@
#include "rf_path.h"
#include <libopencm3/lpc43xx/scu.h>
#include <hackrf_core.h>
#include "hackrf_ui.h"
#include "gpio_lpc.h"
#include "platform_detect.h"
#include "platform_scu.h"
#include "mixer.h"
#include "max283x.h"
#include "max5864.h"
@@ -94,11 +93,6 @@
#define SWITCHCTRL_ANT_PWR (1 << 6) /* turn on antenna port power */
#ifdef HACKRF_ONE
/*
* In HackRF One r9 this control signal has been moved to the microcontroller.
*/
static struct gpio gpio_h1r9_no_ant_pwr = GPIO(2, 4);
static void switchctrl_set_hackrf_one(rf_path_t* const rf_path, uint8_t ctrl)
{
@@ -173,9 +167,9 @@ static void switchctrl_set_hackrf_one(rf_path_t* const rf_path, uint8_t ctrl)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
if (ctrl & SWITCHCTRL_ANT_PWR) {
gpio_clear(&gpio_h1r9_no_ant_pwr);
gpio_clear(rf_path->gpio_h1r9_no_ant_pwr);
} else {
gpio_set(&gpio_h1r9_no_ant_pwr);
gpio_set(rf_path->gpio_h1r9_no_ant_pwr);
}
} else {
if (ctrl & SWITCHCTRL_ANT_PWR) {
@@ -315,32 +309,36 @@ static void switchctrl_set(rf_path_t* const rf_path, const uint8_t gpo)
void rf_path_pin_setup(rf_path_t* const rf_path)
{
#if !defined(JELLYBEAN) && !defined(JAWBREAKER)
const platform_scu_t* scu = platform_scu();
#endif
#ifdef HACKRF_ONE
/* Configure RF switch control signals */
// clang-format off
scu_pinmux(SCU_HP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_LP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_NO_TX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_AMP_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->HP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->LP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->TX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->NO_MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->RX_MIX_BP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->MIX_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->NO_TX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->AMP_BYPASS, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->RX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->NO_RX_AMP_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
// clang-format on
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
scu_pinmux(SCU_H1R9_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_H1R9_NO_ANT_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(&gpio_h1r9_no_ant_pwr);
gpio_output(&gpio_h1r9_no_ant_pwr);
scu_pinmux(SCU_H1R9_NO_VAA_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->H1R9_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->H1R9_NO_ANT_PWR, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(rf_path->gpio_h1r9_no_ant_pwr);
gpio_output(rf_path->gpio_h1r9_no_ant_pwr);
scu_pinmux(scu->H1R9_NO_VAA_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
} else {
scu_pinmux(SCU_TX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->TX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
gpio_output(rf_path->gpio_tx);
scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
}
/*
@@ -365,21 +363,21 @@ void rf_path_pin_setup(rf_path_t* const rf_path)
#elif RAD1O
/* Configure RF switch control signals */
// clang-format off
scu_pinmux(SCU_BY_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_BY_AMP_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_TX_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_RX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_BY_MIX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_BY_MIX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_LOW_HIGH_FILT, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_LOW_HIGH_FILT_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RX_LNA, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(SCU_MIXER_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->BY_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->BY_AMP_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->TX_RX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->TX_RX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->BY_MIX, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->BY_MIX_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->LOW_HIGH_FILT, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->LOW_HIGH_FILT_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->TX_AMP, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->RX_LNA, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->MIXER_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
// clang-format on
/* Configure RF power supply (VAA) switch */
scu_pinmux(SCU_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/*
* Safe (initial) switch settings turn off both amplifiers and antenna port
@@ -401,21 +399,21 @@ void rf_path_pin_setup(rf_path_t* const rf_path)
gpio_output(rf_path->gpio_rx_lna);
#elif PRALINE
/* Configure RF switch control signals */
scu_pinmux(SCU_TX_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->TX_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
board_rev_t rev = detected_revision();
if ((rev == BOARD_REV_PRALINE_R1_0) || (rev == BOARD_REV_GSG_PRALINE_R1_0)) {
scu_pinmux(SCU_MIX_EN_N_R1_0, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
scu_pinmux(scu->MIX_EN_N_R1_0, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
} else {
scu_pinmux(SCU_MIX_EN_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->MIX_EN_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
}
scu_pinmux(SCU_LPF_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(SCU_RF_AMP_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->LPF_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->RF_AMP_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure antenna port power control signal */
scu_pinmux(SCU_ANT_BIAS_EN_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->ANT_BIAS_EN_N, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/* Configure RF power supply (VAA) switch */
scu_pinmux(SCU_NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
scu_pinmux(scu->NO_VAA_ENABLE, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
/*
* Safe (initial) switch settings turn off both amplifiers and antenna port

2
firmware/common/rf_path.h
View File

@@ -60,6 +60,8 @@ typedef struct rf_path_t {
gpio_t gpio_amp_bypass;
gpio_t gpio_rx_amp;
gpio_t gpio_no_rx_amp_pwr;
// In HackRF One r9 this control signal has been moved to the microcontroller.
gpio_t gpio_h1r9_no_ant_pwr;
#endif
#ifdef RAD1O
gpio_t gpio_tx_rx_n;

5
firmware/common/rffc5071.c
View File

@@ -37,9 +37,9 @@
#include "rffc5071_regs.def" // private register def macros
#include "selftest.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "delay.h"
#include "platform_scu.h"
static bool enabled = false;
@@ -104,7 +104,8 @@ void rffc5071_setup(rffc5071_driver_t* const drv)
#ifdef PRALINE
/* Configure mixer PLL lock detect pin */
scu_pinmux(SCU_MIXER_LD, SCU_MIXER_LD_PINCFG);
const platform_scu_t* scu = platform_scu();
scu_pinmux(scu->MIXER_LD, scu->MIXER_LD_PINCFG);
gpio_input(drv->gpio_ld);
#endif

12
firmware/common/rffc5071_spi.c
View File

@@ -20,8 +20,8 @@
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
#include "rffc5071_spi.h"
@@ -65,8 +65,9 @@ static void rffc5071_spi_bus_init(spi_bus_t* const bus)
{
const rffc5071_spi_config_t* const config = bus->config;
scu_pinmux(SCU_MIXER_SCLK, SCU_MIXER_SCLK_PINCFG);
scu_pinmux(SCU_MIXER_SDATA, SCU_MIXER_SDATA_PINCFG);
const platform_scu_t* scu = platform_scu();
scu_pinmux(scu->MIXER_SCLK, scu->MIXER_SCLK_PINCFG);
scu_pinmux(scu->MIXER_SDATA, scu->MIXER_SDATA_PINCFG);
gpio_output(config->gpio_clock);
rffc5071_spi_direction_out(bus);
@@ -80,8 +81,9 @@ static void rffc5071_spi_target_init(spi_bus_t* const bus)
const rffc5071_spi_config_t* const config = bus->config;
/* Configure GPIO pins. */
scu_pinmux(SCU_MIXER_ENX, SCU_GPIO_FAST);
scu_pinmux(SCU_MIXER_RESETX, SCU_GPIO_FAST);
const platform_scu_t* scu = platform_scu();
scu_pinmux(scu->MIXER_ENX, SCU_GPIO_FAST);
scu_pinmux(scu->MIXER_RESETX, SCU_GPIO_FAST);
/* Set GPIO pins as outputs. */
gpio_output(config->gpio_select);

40
firmware/common/sgpio.c
View File

@@ -22,11 +22,11 @@
* Boston, MA 02110-1301, USA.
*/
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/sgpio.h>
#include "hackrf_core.h"
#include "platform_detect.h"
#include "platform_scu.h"
#include "sgpio.h"
@@ -34,29 +34,33 @@ static void update_q_invert(sgpio_config_t* const config);
void sgpio_configure_pin_functions(sgpio_config_t* const config)
{
scu_pinmux(SCU_PINMUX_SGPIO0, SCU_PINMUX_SGPIO0_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO1, SCU_PINMUX_SGPIO1_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO2, SCU_PINMUX_SGPIO2_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO3, SCU_PINMUX_SGPIO3_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO4, SCU_PINMUX_SGPIO4_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO5, SCU_PINMUX_SGPIO5_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO6, SCU_PINMUX_SGPIO6_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO7, SCU_PINMUX_SGPIO7_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO8, SCU_PINMUX_SGPIO8_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO9, SCU_PINMUX_SGPIO9_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO10, SCU_PINMUX_SGPIO10_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO11, SCU_PINMUX_SGPIO11_PINCFG);
scu_pinmux(SCU_PINMUX_SGPIO12, SCU_PINMUX_SGPIO12_PINCFG); /* GPIO0[13] */
scu_pinmux(SCU_PINMUX_SGPIO14, SCU_PINMUX_SGPIO14_PINCFG); /* GPIO5[13] */
scu_pinmux(SCU_PINMUX_SGPIO15, SCU_PINMUX_SGPIO15_PINCFG); /* GPIO5[14] */
const platform_scu_t* scu = platform_scu();
scu_pinmux(scu->PINMUX_SGPIO0, scu->PINMUX_SGPIO0_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO1, scu->PINMUX_SGPIO1_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO2, scu->PINMUX_SGPIO2_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO3, scu->PINMUX_SGPIO3_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO4, scu->PINMUX_SGPIO4_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO5, scu->PINMUX_SGPIO5_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO6, scu->PINMUX_SGPIO6_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO7, scu->PINMUX_SGPIO7_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO8, scu->PINMUX_SGPIO8_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO9, scu->PINMUX_SGPIO9_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO10, scu->PINMUX_SGPIO10_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO11, scu->PINMUX_SGPIO11_PINCFG);
scu_pinmux(scu->PINMUX_SGPIO12, scu->PINMUX_SGPIO12_PINCFG); /* GPIO0[13] */
scu_pinmux(scu->PINMUX_SGPIO14, scu->PINMUX_SGPIO14_PINCFG); /* GPIO5[13] */
scu_pinmux(scu->PINMUX_SGPIO15, scu->PINMUX_SGPIO15_PINCFG); /* GPIO5[14] */
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
#if defined(HACKRF_ONE)
scu_pinmux(
SCU_H1R9_TRIGGER_EN,
scu->H1R9_TRIGGER_EN,
SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[5] */
#endif
} else {
scu_pinmux(
SCU_TRIGGER_EN,
scu->TRIGGER_EN,
SCU_GPIO_FAST | SCU_CONF_FUNCTION4); /* GPIO5[12] */
}

55
firmware/common/si5351c.c
View File

@@ -23,17 +23,10 @@
#include "si5351c.h"
#include "clkin.h"
#include "platform_detect.h"
#include "gpio_lpc.h"
#include "platform_gpio.h"
#include "platform_scu.h"
#include "hackrf_core.h"
#include "selftest.h"
#include <libopencm3/lpc43xx/scu.h>
/* HackRF One r9 clock control */
// clang-format off
static struct gpio gpio_h1r9_clkin_en = GPIO(5, 15);
static struct gpio gpio_h1r9_clkout_en = GPIO(0, 9);
static struct gpio gpio_h1r9_mcu_clk_en = GPIO(0, 8);
// clang-format on
#include <stdbool.h>
@@ -204,20 +197,24 @@ void si5351c_configure_clock_control(
if (source == PLL_SOURCE_CLKIN) {
/* PLLB on CLKIN */
pll = SI5351C_CLK_PLL_SRC_B;
#if defined(HACKRF_ONE)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
/*
* HackRF One r9 always uses PLL A on the XTAL input
* but externally switches that input to CLKIN.
*/
pll = SI5351C_CLK_PLL_SRC_A;
gpio_set(&gpio_h1r9_clkin_en);
gpio_set(platform_gpio()->h1r9_clkin_en);
}
#endif
} else {
/* PLLA on XTAL */
pll = SI5351C_CLK_PLL_SRC_A;
#if defined(HACKRF_ONE)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
gpio_clear(&gpio_h1r9_clkin_en);
gpio_clear(platform_gpio()->h1r9_clkin_en);
}
#endif
}
#endif
if (clkout_enabled) {
@@ -313,11 +310,16 @@ void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
uint8_t data[] = {SI5351C_REG_OUTPUT_EN, value};
si5351c_write(drv, data, sizeof(data));
if ((clkout_enabled) && (detected_platform() == BOARD_ID_HACKRF1_R9)) {
gpio_set(&gpio_h1r9_clkout_en);
} else {
gpio_clear(&gpio_h1r9_clkout_en);
#if defined(HACKRF_ONE)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
const platform_gpio_t* gpio = platform_gpio();
if (clkout_enabled) {
gpio_set(gpio->h1r9_clkout_en);
} else {
gpio_clear(gpio->h1r9_clkout_en);
}
}
#endif
}
void si5351c_set_int_mode(
@@ -409,21 +411,26 @@ void si5351c_init(si5351c_driver_t* const drv)
selftest.report.pass = false;
}
#if defined(HACKRF_ONE)
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
const platform_gpio_t* gpio = platform_gpio();
const platform_scu_t* scu = platform_scu();
/* CLKIN_EN */
scu_pinmux(SCU_H1R9_CLKIN_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
gpio_clear(&gpio_h1r9_clkin_en);
gpio_output(&gpio_h1r9_clkin_en);
scu_pinmux(scu->H1R9_CLKIN_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
gpio_clear(gpio->h1r9_clkin_en);
gpio_output(gpio->h1r9_clkin_en);
/* CLKOUT_EN */
scu_pinmux(SCU_H1R9_CLKOUT_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(&gpio_h1r9_clkout_en);
gpio_output(&gpio_h1r9_clkout_en);
scu_pinmux(scu->H1R9_CLKOUT_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(gpio->h1r9_clkout_en);
gpio_output(gpio->h1r9_clkout_en);
/* MCU_CLK_EN */
scu_pinmux(SCU_H1R9_MCU_CLK_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(&gpio_h1r9_mcu_clk_en);
gpio_output(&gpio_h1r9_mcu_clk_en);
scu_pinmux(scu->H1R9_MCU_CLK_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
gpio_clear(gpio->h1r9_mcu_clk_en);
gpio_output(gpio->h1r9_mcu_clk_en);
}
#endif
(void) drv;
}

17
firmware/common/w25q80bv_target.c
View File

@@ -22,8 +22,7 @@
#include "w25q80bv_target.h"
#include <libopencm3/lpc43xx/scu.h>
#include "hackrf_core.h"
#include "platform_scu.h"
/* TODO: Why is CS being controlled manually when SSP0 could do it
* automatically?
@@ -35,6 +34,8 @@ void w25q80bv_target_init(w25q80bv_driver_t* const drv)
/* Init SPIFI GPIO to Normal GPIO */
const platform_scu_t* scu = platform_scu();
// P3_3 SPIFI_SCK => SSP0_SCK
scu_pinmux(P3_3, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
// P3_4 SPIFI SPIFI_SIO3 IO3 => GPIO1[14]
@@ -49,14 +50,14 @@ void w25q80bv_target_init(w25q80bv_driver_t* const drv)
scu_pinmux(P3_8, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4));
/* configure SSP pins */
scu_pinmux(SCU_SSP0_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP0_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP0_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
scu_pinmux(scu->SSP0_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP0_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(scu->SSP0_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
/* configure GPIO pins */
scu_pinmux(SCU_FLASH_HOLD, SCU_GPIO_FAST);
scu_pinmux(SCU_FLASH_WP, SCU_GPIO_FAST);
scu_pinmux(SCU_SSP0_CS, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4));
scu_pinmux(scu->FLASH_HOLD, SCU_GPIO_FAST);
scu_pinmux(scu->FLASH_WP, SCU_GPIO_FAST);
scu_pinmux(scu->SSP0_CS, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4));
/* drive CS, HOLD, and WP pins high */
gpio_set(drv->gpio_hold);

11
firmware/hackrf_usb/usb_api_board_info.c
View File

@@ -23,6 +23,7 @@
#include "usb_api_board_info.h"
#include "platform_detect.h"
#include "platform_gpio.h"
#include "firmware_info.h"
#include <hackrf_core.h>
@@ -35,9 +36,6 @@
#ifdef HACKRF_ONE
#include "gpio_lpc.h"
static struct gpio gpio_h1r9_clkout_en = GPIO(0, 9);
static struct gpio gpio_h1r9_mcu_clk_en = GPIO(0, 8);
static struct gpio gpio_h1r9_rx = GPIO(0, 7);
#endif
usb_request_status_t usb_vendor_request_read_board_id(
@@ -138,9 +136,10 @@ usb_request_status_t usb_vendor_request_reset(
* correctly after the reset.
*/
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
gpio_input(&gpio_h1r9_mcu_clk_en);
gpio_input(&gpio_h1r9_clkout_en);
gpio_input(&gpio_h1r9_rx);
const platform_gpio_t* gpio = platform_gpio();
gpio_input(gpio->h1r9_mcu_clk_en);
gpio_input(gpio->h1r9_clkout_en);
gpio_input(gpio->h1r9_rx);
}
#endif
wwdt_reset(100000);