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fix gateware typo and update build, no DC block in loopback test (#1621)

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This commit is contained in:
Diego Hurtado
2025-12-17 20:33:06 +01:00
committed by GitHub
parent 1925e5908a
commit 4ed9169f4e
3 changed files with 3 additions and 5 deletions
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6
firmware/common/fpga.c
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@@ -273,9 +273,8 @@ bool fpga_if_xcvr_selftest()
// Set common RX path and gateware settings for the measurements.
ssp1_set_mode_ice40();
ice40_spi_write(&ice40, 0x01, 0x1); // RX DC block
ice40_spi_write(&ice40, 0x05, 64); // NCO phase increment
ice40_spi_write(&ice40, 0x03, 1); // NCO TX enable
ice40_spi_write(&ice40, 0x05, 64); // NCO phase increment
ice40_spi_write(&ice40, 0x03, 1); // NCO TX enable
ssp1_set_mode_max283x();
rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_RX_CALIBRATION);
max2831_set_lna_gain(&max283x, 16);
@@ -335,7 +334,6 @@ bool fpga_if_xcvr_selftest()
rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_OFF);
narrowband_filter_set(0);
ssp1_set_mode_ice40();
ice40_spi_write(&ice40, 0x01, 0);
ice40_spi_write(&ice40, 0x03, 0);
ssp1_set_mode_max283x();

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firmware/fpga/build/praline_fpga.bin
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2
firmware/fpga/dsp/cic.py
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@@ -75,7 +75,7 @@ class CICInterpolator(wiring.Component):
if list(self.rates) != [1]:
if inner_zoh:
_ = next(bit_growths), next(bit_growths) # drop comb and integrator growths
stage = factor_reset(Upsampler(self.num_channels * width, max(self.rate), zero_order_hold=inner_zoh, variable=True, always_ready=always_ready))
stage = factor_reset(Upsampler(self.num_channels * width, max(self.rates), zero_order_hold=inner_zoh, variable=True, always_ready=always_ready))
m.submodules["upsampler"] = stage
m.d.sync += stage.factor.eq(1 << self.factor)
stages += [ stage ]