diff --git a/firmware/common/fpga.c b/firmware/common/fpga.c
index 9a87daf6..05585b29 100644
--- a/firmware/common/fpga.c
+++ b/firmware/common/fpga.c
@@ -273,9 +273,8 @@ bool fpga_if_xcvr_selftest()
 
 	// Set common RX path and gateware settings for the measurements.
 	ssp1_set_mode_ice40();
-	ice40_spi_write(&ice40, 0x01, 0x1); // RX DC block
-	ice40_spi_write(&ice40, 0x05, 64);  // NCO phase increment
-	ice40_spi_write(&ice40, 0x03, 1);   // NCO TX enable
+	ice40_spi_write(&ice40, 0x05, 64); // NCO phase increment
+	ice40_spi_write(&ice40, 0x03, 1);  // NCO TX enable
 	ssp1_set_mode_max283x();
 	rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_RX_CALIBRATION);
 	max2831_set_lna_gain(&max283x, 16);
@@ -335,7 +334,6 @@ bool fpga_if_xcvr_selftest()
 	rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_OFF);
 	narrowband_filter_set(0);
 	ssp1_set_mode_ice40();
-	ice40_spi_write(&ice40, 0x01, 0);
 	ice40_spi_write(&ice40, 0x03, 0);
 	ssp1_set_mode_max283x();
 
diff --git a/firmware/fpga/build/praline_fpga.bin b/firmware/fpga/build/praline_fpga.bin
index ef0704ca..8279693b 100644
Binary files a/firmware/fpga/build/praline_fpga.bin and b/firmware/fpga/build/praline_fpga.bin differ
diff --git a/firmware/fpga/dsp/cic.py b/firmware/fpga/dsp/cic.py
index 6f7bf74e..fa0f3fa0 100644
--- a/firmware/fpga/dsp/cic.py
+++ b/firmware/fpga/dsp/cic.py
@@ -75,7 +75,7 @@ class CICInterpolator(wiring.Component):
         if list(self.rates) != [1]:
             if inner_zoh:
                 _ = next(bit_growths), next(bit_growths)  # drop comb and integrator growths
-            stage = factor_reset(Upsampler(self.num_channels * width, max(self.rate), zero_order_hold=inner_zoh, variable=True, always_ready=always_ready))
+            stage = factor_reset(Upsampler(self.num_channels * width, max(self.rates), zero_order_hold=inner_zoh, variable=True, always_ready=always_ready))
             m.submodules["upsampler"] = stage
             m.d.sync += stage.factor.eq(1 << self.factor)
             stages += [ stage ]