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firmware: exclude signals not used by praline

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This commit is contained in:
Antoine van Gelder
2026-03-23 10:48:31 +02:00
parent ce5cd7b052
commit 0c5b893868
5 changed files with 14 additions and 16 deletions
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2
firmware/common/hackrf_core.c
View File

@@ -848,7 +848,7 @@ void pin_setup(void)
#endif
jtag_gpio_cpld.gpio_tck = gpio->cpld_tck;
#if !defined(PRALINE)
#if defined(HACKRF_ONE) || defined(RAD1O)
jtag_gpio_cpld.gpio_tms = gpio->cpld_tms;
jtag_gpio_cpld.gpio_tdi = gpio->cpld_tdi;
jtag_gpio_cpld.gpio_tdo = gpio->cpld_tdo;

14
firmware/common/platform_gpio.c
View File

@@ -74,11 +74,11 @@ const platform_gpio_t* platform_gpio(void)
/* RF supply (VAA) control */
#if defined(HACKRF_ONE)
gpio.vaa_disable = &GPIO2_9;
gpio.vaa_disable = &GPIO2_9;
#elif defined(PRALINE)
gpio.vaa_disable = &GPIO4_1;
gpio.vaa_disable = &GPIO4_1;
#elif defined(RAD1O)
gpio.vaa_enable = &GPIO2_9;
gpio.vaa_enable = &GPIO2_9;
#endif
/* W25Q80BV Flash */
@@ -131,13 +131,11 @@ const platform_gpio_t* platform_gpio(void)
gpio.fpga_cfg_creset = &GPIO2_11;
gpio.fpga_cfg_cdone = &GPIO5_14;
gpio.fpga_cfg_spi_cs = &GPIO2_10;
#elif defined(HACKRF_ONE) || defined(RAD1O)
#endif
#if defined(HACKRF_ONE) || defined(RAD1O)
gpio.cpld_tdo = &GPIO5_18;
gpio.cpld_tms = &GPIO3_4;
gpio.cpld_tdi = &GPIO3_1;
#else
gpio.cpld_tms = &GPIO3_1;
gpio.cpld_tdi = &GPIO3_4;
#endif
#if defined(HACKRF_ONE) || defined(PRALINE)
gpio.cpld_pp_tms = &GPIO1_1;
@@ -192,9 +190,7 @@ const platform_gpio_t* platform_gpio(void)
gpio.h1r9_clkin_en = &GPIO5_15;
gpio.h1r9_clkout_en = &GPIO0_9;
gpio.h1r9_mcu_clk_en = &GPIO0_8;
}
if (detected_platform() == BOARD_ID_HACKRF1_R9) {
gpio.h1r9_1v8_enable = &GPIO2_9;
gpio.h1r9_vaa_disable = &GPIO3_6;
gpio.h1r9_trigger_enable = &GPIO5_5;

2
firmware/common/platform_gpio.h
View File

@@ -110,9 +110,11 @@ typedef struct {
/* CPLD JTAG interface GPIO pins, FPGA config pins in Praline */
gpio_t cpld_tck;
#if defined(HACKRF_ONE) || defined(RAD1O)
gpio_t cpld_tdo;
gpio_t cpld_tms;
gpio_t cpld_tdi;
#endif
#if defined(HACKRF_ONE) || defined(PRALINE)
gpio_t cpld_pp_tms;
gpio_t cpld_pp_tdo;

7
firmware/common/platform_scu.c
View File

@@ -77,16 +77,15 @@ const platform_scu_t* platform_scu(void)
scu.SSP1_CS = (P1_20); /* P1_20 */
/* CPLD JTAG interface */
scu.PINMUX_CPLD_TCK = (P6_1); /* GPIO3[ 0] */
#if defined(PRALINE)
scu.PINMUX_FPGA_CRESET = (P5_2); /* GPIO2[11] on P5_2 */
scu.PINMUX_FPGA_CDONE = (P4_10); /* GPIO5[14] */
scu.PINMUX_FPGA_SPI_CS = (P5_1); /* GPIO2[10] */
#endif
scu.PINMUX_CPLD_TDO = (P9_5); /* GPIO5[18] */
scu.PINMUX_CPLD_TCK = (P6_1); /* GPIO3[ 0] */
#if defined(RAD1O) || defined(HACKRF_ONE) || defined(PRALINE)
#elif defined(RAD1O) || defined(HACKRF_ONE)
scu.PINMUX_CPLD_TMS = (P6_5); /* GPIO3[ 4] */
scu.PINMUX_CPLD_TDI = (P6_2); /* GPIO3[ 1] */
scu.PINMUX_CPLD_TDO = (P9_5); /* GPIO5[18] */
#else
scu.PINMUX_CPLD_TMS = (P6_2); /* GPIO3[ 1] */
scu.PINMUX_CPLD_TDI = (P6_5); /* GPIO3[ 4] */

5
firmware/common/platform_scu.h
View File

@@ -80,11 +80,12 @@ typedef struct {
scu_grp_pin_t PINMUX_FPGA_CRESET;
scu_grp_pin_t PINMUX_FPGA_CDONE;
scu_grp_pin_t PINMUX_FPGA_SPI_CS;
#endif
#else
scu_grp_pin_t PINMUX_CPLD_TDO;
scu_grp_pin_t PINMUX_CPLD_TCK;
scu_grp_pin_t PINMUX_CPLD_TMS;
scu_grp_pin_t PINMUX_CPLD_TDI;
#endif
scu_grp_pin_t PINMUX_CPLD_TCK;
/* CPLD SGPIO interface */
scu_grp_pin_t PINMUX_SGPIO0;