mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-03-24 16:18:06 +01:00
311 lines
8.1 KiB
C
311 lines
8.1 KiB
C
/*
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* Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __PLATFORM_SCU_H
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#define __PLATFORM_SCU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <libopencm3/lpc43xx/scu.h>
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#include "platform_detect.h"
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/*
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* SCU PinMux
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*/
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typedef struct {
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/* LED PinMux */
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scu_grp_pin_t PINMUX_LED1;
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scu_grp_pin_t PINMUX_LED2;
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scu_grp_pin_t PINMUX_LED3;
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#if defined(RAD1O) || defined(PRALINE)
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scu_grp_pin_t PINMUX_LED4;
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#endif
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/* Power Supply PinMux */
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scu_grp_pin_t PINMUX_EN1V8;
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scu_grp_pin_t PINMUX_EN1V2;
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#if defined(PRALINE)
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scu_grp_pin_t PINMUX_EN3V3_AUX_N;
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scu_grp_pin_t PINMUX_EN3V3_OC_N;
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#endif
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/* GPIO Input PinMux */
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scu_grp_pin_t PINMUX_BOOT0;
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scu_grp_pin_t PINMUX_BOOT1;
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#if !defined(HACKRF_ONE)
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scu_grp_pin_t PINMUX_BOOT2;
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scu_grp_pin_t PINMUX_BOOT3;
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#endif
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scu_grp_pin_t PINMUX_PP_LCD_TE;
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scu_grp_pin_t PINMUX_PP_LCD_RDX;
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scu_grp_pin_t PINMUX_PP_UNUSED;
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scu_grp_pin_t PINMUX_PP_LCD_WRX;
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scu_grp_pin_t PINMUX_PP_DIR;
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/* USB peripheral */
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#if defined(JAWBREAKER)
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scu_grp_pin_t PINMUX_USB_LED0;
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scu_grp_pin_t PINMUX_USB_LED1;
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#endif
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/* SSP1 Peripheral PinMux */
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scu_grp_pin_t SSP1_CIPO;
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scu_grp_pin_t SSP1_COPI;
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scu_grp_pin_t SSP1_SCK;
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scu_grp_pin_t SSP1_CS;
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/* CPLD JTAG interface */
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#if defined(PRALINE)
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scu_grp_pin_t PINMUX_FPGA_CRESET;
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scu_grp_pin_t PINMUX_FPGA_CDONE;
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scu_grp_pin_t PINMUX_FPGA_SPI_CS;
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#else
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scu_grp_pin_t PINMUX_CPLD_TDO;
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scu_grp_pin_t PINMUX_CPLD_TMS;
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scu_grp_pin_t PINMUX_CPLD_TDI;
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#endif
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scu_grp_pin_t PINMUX_CPLD_TCK;
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/* CPLD SGPIO interface */
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scu_grp_pin_t PINMUX_SGPIO0;
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scu_grp_pin_t PINMUX_SGPIO1;
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scu_grp_pin_t PINMUX_SGPIO2;
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scu_grp_pin_t PINMUX_SGPIO3;
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scu_grp_pin_t PINMUX_SGPIO4;
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scu_grp_pin_t PINMUX_SGPIO5;
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scu_grp_pin_t PINMUX_SGPIO6;
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scu_grp_pin_t PINMUX_SGPIO7;
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scu_grp_pin_t PINMUX_SGPIO8;
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scu_grp_pin_t PINMUX_SGPIO9;
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scu_grp_pin_t PINMUX_SGPIO10;
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scu_grp_pin_t PINMUX_SGPIO11;
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scu_grp_pin_t PINMUX_SGPIO12;
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scu_grp_pin_t PINMUX_SGPIO14;
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scu_grp_pin_t PINMUX_SGPIO15;
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scu_grp_pin_t PINMUX_SGPIO0_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO1_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO2_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO3_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO4_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO5_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO6_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO7_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO8_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO9_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO10_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO11_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO12_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO14_PINCFG;
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scu_grp_pin_t PINMUX_SGPIO15_PINCFG;
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scu_grp_pin_t TRIGGER_EN;
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/* MAX283x GPIO (XCVR_CTL) PinMux */
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scu_grp_pin_t XCVR_RXHP; // RAD1O, PRALINE
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scu_grp_pin_t XCVR_B6; // RAD1O
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scu_grp_pin_t XCVR_B7; // RAD1O
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scu_grp_pin_t XCVR_ENABLE; // PRALINE, HACKRF_ONE
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scu_grp_pin_t XCVR_RXENABLE; // PRALINE, HACKRF_ONE
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scu_grp_pin_t XCVR_CS; // PRALINE, HACKRF_ONE
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scu_grp_pin_t XCVR_LD; // PRALINE
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uint32_t XCVR_ENABLE_PINCFG; // PRALINE, HACKRF_ONE
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uint32_t XCVR_RXENABLE_PINCFG; // PRALINE, HACKRF_ONE
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uint32_t XCVR_CS_PINCFG; // PRALINE, HACKRF_ONE
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uint32_t XCVR_RXHP_PINCFG; // PRALINE
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uint32_t XCVR_LD_PINCFG; // PRALINE
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scu_grp_pin_t XCVR_TXENABLE; // HACKRF_ONE
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uint32_t XCVR_TXENABLE_PINCFG; // HACKRF_ONE
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/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
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scu_grp_pin_t AD_CS;
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scu_grp_pin_t AD_CS_PINCFG;
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/* RFFC5071 GPIO serial interface PinMux */
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scu_grp_pin_t MIXER_ENX;
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scu_grp_pin_t MIXER_SCLK;
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scu_grp_pin_t MIXER_SDATA;
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scu_grp_pin_t MIXER_RESETX;
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uint32_t MIXER_SCLK_PINCFG;
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uint32_t MIXER_SDATA_PINCFG;
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#if defined(PRALINE)
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scu_grp_pin_t MIXER_LD;
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uint32_t MIXER_LD_PINCFG;
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#elif defined(RAD1O)
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scu_grp_pin_t VCO_CE;
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scu_grp_pin_t VCO_SCLK;
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scu_grp_pin_t VCO_SDATA;
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scu_grp_pin_t VCO_LE;
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scu_grp_pin_t VCO_MUX;
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scu_grp_pin_t MIXER_EN;
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scu_grp_pin_t SYNT_RFOUT_EN;
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#endif
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/* RF LDO control */
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#if defined(JAWBREAKER)
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scu_grp_pin_t RF_LDO_ENABLE;
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#endif
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/* RF supply (VAA) control */
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#if defined(PRALINE) || defined(HACKRF_ONE)
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scu_grp_pin_t NO_VAA_ENABLE;
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#elif defined(RAD1O)
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scu_grp_pin_t VAA_ENABLE;
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#endif
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/* SPI flash */
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scu_grp_pin_t SSP0_CIPO;
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scu_grp_pin_t SSP0_COPI;
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scu_grp_pin_t SSP0_SCK;
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scu_grp_pin_t SSP0_CS;
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scu_grp_pin_t FLASH_HOLD;
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scu_grp_pin_t FLASH_WP;
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/* RF switch control */
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#if defined(PRALINE)
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scu_grp_pin_t TX_EN;
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scu_grp_pin_t MIX_EN_N;
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scu_grp_pin_t MIX_EN_N_R1_0;
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scu_grp_pin_t LPF_EN;
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scu_grp_pin_t RF_AMP_EN;
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scu_grp_pin_t ANT_BIAS_EN_N;
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scu_grp_pin_t ANT_BIAS_OC_N;
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#elif defined(HACKRF_ONE)
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scu_grp_pin_t HP;
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scu_grp_pin_t LP;
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scu_grp_pin_t TX_MIX_BP;
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scu_grp_pin_t NO_MIX_BYPASS;
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scu_grp_pin_t RX_MIX_BP;
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scu_grp_pin_t TX_AMP;
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scu_grp_pin_t TX;
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scu_grp_pin_t MIX_BYPASS;
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scu_grp_pin_t RX;
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scu_grp_pin_t NO_TX_AMP_PWR;
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scu_grp_pin_t AMP_BYPASS;
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scu_grp_pin_t RX_AMP;
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scu_grp_pin_t NO_RX_AMP_PWR;
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#elif defined(RAD1O)
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scu_grp_pin_t BY_AMP;
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scu_grp_pin_t BY_AMP_N;
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scu_grp_pin_t TX_RX;
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scu_grp_pin_t TX_RX_N;
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scu_grp_pin_t BY_MIX;
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scu_grp_pin_t BY_MIX_N;
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scu_grp_pin_t LOW_HIGH_FILT;
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scu_grp_pin_t LOW_HIGH_FILT_N;
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scu_grp_pin_t TX_AMP;
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scu_grp_pin_t RX_LNA;
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#endif
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/* Praline */
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#if defined(PRALINE)
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scu_grp_pin_t P2_CTRL0;
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scu_grp_pin_t P2_CTRL1;
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scu_grp_pin_t P1_CTRL0;
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scu_grp_pin_t P1_CTRL1;
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scu_grp_pin_t P1_CTRL2;
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scu_grp_pin_t CLKIN_CTRL;
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scu_grp_pin_t AA_EN;
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scu_grp_pin_t TRIGGER_IN;
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scu_grp_pin_t TRIGGER_OUT;
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scu_grp_pin_t PPS_OUT;
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scu_grp_pin_t P2_CTRL0_PINCFG;
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scu_grp_pin_t P2_CTRL1_PINCFG;
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scu_grp_pin_t P1_CTRL0_PINCFG;
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scu_grp_pin_t P1_CTRL1_PINCFG;
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scu_grp_pin_t P1_CTRL2_PINCFG;
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scu_grp_pin_t CLKIN_CTRL_PINCFG;
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scu_grp_pin_t AA_EN_PINCFG;
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scu_grp_pin_t TRIGGER_IN_PINCFG;
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scu_grp_pin_t TRIGGER_OUT_PINCFG;
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scu_grp_pin_t PPS_OUT_PINCFG;
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#endif
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/* HackRF One r9 */
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#if defined(HACKRF_ONE)
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scu_grp_pin_t H1R9_CLKIN_EN;
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scu_grp_pin_t H1R9_CLKOUT_EN;
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scu_grp_pin_t H1R9_MCU_CLK_EN;
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scu_grp_pin_t H1R9_RX;
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scu_grp_pin_t H1R9_NO_ANT_PWR;
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scu_grp_pin_t H1R9_EN1V8;
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scu_grp_pin_t H1R9_NO_VAA_EN;
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scu_grp_pin_t H1R9_TRIGGER_EN;
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#endif
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/* Miscellaneous */
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scu_grp_pin_t PINMUX_PP_D0;
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scu_grp_pin_t PINMUX_PP_D1;
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scu_grp_pin_t PINMUX_PP_D2;
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scu_grp_pin_t PINMUX_PP_D3;
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scu_grp_pin_t PINMUX_PP_D4;
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scu_grp_pin_t PINMUX_PP_D5;
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scu_grp_pin_t PINMUX_PP_D6;
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scu_grp_pin_t PINMUX_PP_D7;
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/* TODO add other Pins */
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scu_grp_pin_t PINMUX_GPIO3_8;
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scu_grp_pin_t PINMUX_GPIO3_9;
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scu_grp_pin_t PINMUX_GPIO3_10;
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scu_grp_pin_t PINMUX_GPIO3_11;
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scu_grp_pin_t PINMUX_GPIO3_12;
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scu_grp_pin_t PINMUX_GPIO3_13;
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scu_grp_pin_t PINMUX_GPIO3_14;
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scu_grp_pin_t PINMUX_GPIO3_15;
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scu_grp_pin_t PINMUX_PP_TDO;
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scu_grp_pin_t PINMUX_SD_POW;
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scu_grp_pin_t PINMUX_SD_CMD;
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scu_grp_pin_t PINMUX_PP_TMS;
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scu_grp_pin_t PINMUX_SD_VOLT0;
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scu_grp_pin_t PINMUX_SD_DAT0;
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scu_grp_pin_t PINMUX_SD_DAT1;
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scu_grp_pin_t PINMUX_SD_DAT2;
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scu_grp_pin_t PINMUX_SD_DAT3;
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scu_grp_pin_t PINMUX_SD_CD;
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scu_grp_pin_t PINMUX_PP_IO_STBX;
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scu_grp_pin_t PINMUX_PP_ADDR;
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scu_grp_pin_t PINMUX_U0_TXD;
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scu_grp_pin_t PINMUX_U0_RXD;
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scu_grp_pin_t PINMUX_ISP;
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scu_grp_pin_t PINMUX_GP_CLKIN;
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} platform_scu_t;
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// Detects and returns the global platform scu instance of the active board id and revision.
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const platform_scu_t* platform_scu(void);
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// Platform detection needs these for error indication.
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#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
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#define SCU_PINMUX_LED2 (P4_2) /* GPIO2[2] on P4_2 */
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#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PLATFORM_SCU_H */
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