Mirrors/hackrf
2
0
Fork 0
mirror of https://github.com/greatscottgadgets/hackrf.git synced 2026-03-03 05:55:18 +01:00
Code Issues Packages Projects Releases Wiki Activity

Implement automatic offset tuning

Browse Source 
Add RX tuning table
This commit is contained in:
Michael Ossmann
2025-12-30 21:34:03 -05:00
parent 7e1c17593d
commit fc4b9aca68
5 changed files with 372 additions and 185 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
firmware/common/fpga.h
View File

@@ -23,7 +23,7 @@
#define __FPGA_H
#include <stdbool.h>
#include "hackrf_core.h"
#include "ice40_spi.h"
/* Up to 6 registers, each containing up to 8 bits of data */
#define FPGA_NUM_REGS 6

13
firmware/common/radio.c
View File

@@ -225,6 +225,13 @@ radio_error_t radio_set_frequency(
frequency.if_hz,
frequency.lo_hz,
frequency.path);
#ifdef PRALINE
if (ok) {
fpga_set_rx_quarter_shift_mode(
&fpga,
FPGA_QUARTER_SHIFT_MODE_NONE);
}
#endif
if (!ok) {
return RADIO_ERR_INVALID_PARAM;
}
@@ -272,7 +279,11 @@ radio_error_t radio_set_frequency(
return RADIO_ERR_INVALID_PARAM;
}
ok = tuning_set_frequency(tune_config, frequency.hz);
fpga_set_rx_quarter_shift_mode(&fpga, tune_config->shift);
uint32_t offset = (config->sample_rate[RADIO_SAMPLE_RATE_CLOCKGEN].hz
<< config->resampling_n) /
8;
ok = tuning_set_frequency(tune_config, frequency.hz, offset);
#endif
if (!ok) {
return RADIO_ERR_INVALID_PARAM;

507
firmware/common/tune_config.h
View File

@@ -23,195 +23,354 @@
#define __TUNE_CONFIG_H__
#ifdef PRALINE
#include "fpga.h"
typedef struct {
uint16_t rf_range_end_mhz;
uint16_t if_mhz;
bool high_lo;
fpga_quarter_shift_mode_t shift;
} tune_config_t;
// clang-format off
/* tuning table optimized for TX */
static const tune_config_t max2831_tune_config_tx[] = {
{ 2100, 2375, true },
{ 2175, 2325, false },
{ 2320, 2525, false },
{ 2580, 0, false },
{ 3000, 2325, false },
{ 3100, 2375, false },
{ 3200, 2425, false },
{ 3350, 2375, false },
{ 3500, 2475, false },
{ 3550, 2425, false },
{ 3650, 2325, false },
{ 3700, 2375, false },
{ 3850, 2425, false },
{ 3925, 2375, false },
{ 4600, 2325, false },
{ 4700, 2375, false },
{ 4800, 2425, false },
{ 5100, 2375, false },
{ 5850, 2525, false },
{ 6500, 2325, false },
{ 6750, 2375, false },
{ 6850, 2425, false },
{ 6950, 2475, false },
{ 7000, 2525, false },
{ 7251, 2575, false },
{ 0, 0, false },
{ 2100, 2375, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2175, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2320, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2580, 0, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3000, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3100, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3200, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3350, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3500, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3550, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3650, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3700, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3850, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3925, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4600, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4700, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4800, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5100, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5850, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6500, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6750, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6850, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6950, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 7000, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 7251, 2575, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 0, 0, false, 0 },
};
/* tuning table optimized for 20 Msps interleaved RX sweep mode */
static const tune_config_t max2831_tune_config_rx_sweep[] = {
{ 140, 2330, false },
{ 424, 2570, true },
{ 557, 2520, true },
{ 593, 2380, true },
{ 776, 2360, true },
{ 846, 2570, true },
{ 926, 2500, true },
{ 1055, 2380, true },
{ 1175, 2360, true },
{ 1391, 2340, true },
{ 1529, 2570, true },
{ 1671, 2520, true },
{ 1979, 2380, true },
{ 2150, 2330, true },
{ 2160, 2550, false },
{ 2170, 2560, false },
{ 2179, 2570, false },
{ 2184, 2520, false },
{ 2187, 2560, false },
{ 2194, 2530, false },
{ 2203, 2540, false },
{ 2212, 2550, false },
{ 2222, 2560, false },
{ 2231, 2570, false },
{ 2233, 2530, false },
{ 2237, 2520, false },
{ 2241, 2550, false },
{ 2245, 2570, false },
{ 2250, 2560, false },
{ 2252, 2550, false },
{ 2258, 2570, false },
{ 2261, 2560, false },
{ 2266, 2540, false },
{ 2271, 2570, false },
{ 2275, 2550, false },
{ 2280, 2500, false },
{ 2284, 2560, false },
{ 2285, 2530, false },
{ 2289, 2510, false },
{ 2293, 2570, false },
{ 2294, 2540, false },
{ 2298, 2520, false },
{ 2301, 2570, false },
{ 2302, 2550, false },
{ 2307, 2530, false },
{ 2308, 2560, false },
{ 2312, 2560, false },
{ 2316, 2540, false },
{ 2317, 2570, false },
{ 2320, 2570, false },
{ 2580, 0, false },
{ 2585, 2360, false },
{ 2588, 2340, false },
{ 2594, 2350, false },
{ 2606, 2330, false },
{ 2617, 2340, false },
{ 2627, 2350, false },
{ 2638, 2360, false },
{ 2649, 2370, false },
{ 2659, 2380, false },
{ 2664, 2350, false },
{ 2675, 2360, false },
{ 2686, 2370, false },
{ 2697, 2380, false },
{ 2705, 2350, false },
{ 2716, 2360, false },
{ 2728, 2370, false },
{ 2739, 2380, false },
{ 2757, 2330, false },
{ 2779, 2350, false },
{ 2790, 2360, false },
{ 2801, 2370, false },
{ 2812, 2380, false },
{ 2821, 2570, false },
{ 2831, 2520, false },
{ 2852, 2330, false },
{ 2874, 2350, false },
{ 2897, 2370, false },
{ 2913, 2510, false },
{ 2925, 2570, false },
{ 2937, 2530, false },
{ 2948, 2540, false },
{ 2960, 2550, false },
{ 2975, 2330, false },
{ 2988, 2340, false },
{ 3002, 2330, false },
{ 3014, 2360, false },
{ 3027, 2370, false },
{ 3041, 2500, false },
{ 3052, 2510, false },
{ 3064, 2520, false },
{ 3082, 2500, false },
{ 3107, 2520, false },
{ 3132, 2540, false },
{ 3157, 2560, false },
{ 3170, 2570, false },
{ 3192, 2500, false },
{ 3216, 2340, false },
{ 3270, 2330, false },
{ 3319, 2370, false },
{ 3341, 2340, false },
{ 3370, 2330, false },
{ 3400, 2350, false },
{ 3430, 2370, false },
{ 3464, 2520, false },
{ 3491, 2540, false },
{ 3519, 2560, false },
{ 3553, 2510, false },
{ 3595, 2540, false },
{ 3638, 2570, false },
{ 3665, 2540, false },
{ 3685, 2560, false },
{ 3726, 2330, false },
{ 3790, 2370, false },
{ 3910, 2350, false },
{ 4014, 2510, false },
{ 4123, 2380, false },
{ 4191, 2550, false },
{ 4349, 2510, false },
{ 4452, 2570, false },
{ 4579, 2500, false },
{ 4707, 2570, false },
{ 4831, 2560, false },
{ 4851, 2570, false },
{ 4871, 2560, false },
{ 4891, 2570, false },
{ 4911, 2540, false },
{ 4931, 2550, false },
{ 4951, 2560, false },
{ 5044, 2330, false },
{ 5065, 2340, false },
{ 5174, 2330, false },
{ 5285, 2380, false },
{ 5449, 2340, false },
{ 5574, 2510, false },
{ 5717, 2340, false },
{ 5892, 2530, false },
{ 6096, 2350, false },
{ 6254, 2560, false },
{ 6625, 2340, false },
{ 6764, 2540, false },
{ 6930, 2530, false },
{ 7251, 2570, false },
{ 0, 0, false },
{ 140, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 424, 2570, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 557, 2520, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 593, 2380, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 776, 2360, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 846, 2570, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 926, 2500, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1055, 2380, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1175, 2360, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1391, 2340, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1529, 2570, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1671, 2520, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 1979, 2380, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2150, 2330, true, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2160, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2170, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2179, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2184, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2187, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2194, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2203, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2212, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2222, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2231, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2233, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2237, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2241, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2245, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2250, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2252, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2258, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2261, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2266, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2271, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2275, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2280, 2500, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2284, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2285, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2289, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2293, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2294, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2298, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2301, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2302, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2307, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2308, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2312, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2316, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2317, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2320, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2580, 0, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2585, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2588, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2594, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2606, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2617, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2627, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2638, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2649, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2659, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2664, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2675, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2686, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2697, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2705, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2716, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2728, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2739, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2757, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2779, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2790, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2801, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2812, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2821, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2831, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2852, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2874, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2897, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2913, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2925, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2937, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2948, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2960, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2975, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 2988, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3002, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3014, 2360, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3027, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3041, 2500, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3052, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3064, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3082, 2500, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3107, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3132, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3157, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3170, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3192, 2500, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3216, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3270, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3319, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3341, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3370, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3400, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3430, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3464, 2520, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3491, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3519, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3553, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3595, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3638, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3665, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3685, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3726, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3790, 2370, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 3910, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4014, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4123, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4191, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4349, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4452, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4579, 2500, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4707, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4831, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4851, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4871, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4891, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4911, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4931, 2550, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 4951, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5044, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5065, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5174, 2330, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5285, 2380, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5449, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5574, 2510, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5717, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 5892, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6096, 2350, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6254, 2560, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6625, 2340, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6764, 2540, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 6930, 2530, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 7251, 2570, false, FPGA_QUARTER_SHIFT_MODE_NONE },
{ 0, 0, false, 0 },
};
// TODO these are just copies of max2831_tune_config_rx_sweep for now
#define max2831_tune_config_rx max2831_tune_config_rx_sweep
// clang-format on
/* tuning table optimized for RX */
static const tune_config_t max2831_tune_config_rx[] = {
{ 50, 2320, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 100, 2320, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 140, 2320, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 406, 2560, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 511, 2380, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 578, 2560, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 741, 2340, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 861, 2560, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 921, 2560, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 1049, 2340, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 1169, 2380, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 1360, 2340, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 1544, 2560, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 1675, 2560, true, FPGA_QUARTER_SHIFT_MODE_UP },
{ 1992, 2380, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2070, 2340, true, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2161, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2180, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2188, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2194, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2195, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2205, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2213, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2215, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2222, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2232, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2234, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2240, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2245, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2247, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2251, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2257, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2258, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2262, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2265, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2270, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2275, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2279, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2280, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2282, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2284, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2289, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2292, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2293, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2299, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2300, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2302, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2307, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2315, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2320, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2380, 0, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2440, 0, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2500, 0, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2580, 0, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2583, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2584, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2587, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2593, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2607, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2609, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2615, 2360, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2627, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2629, 2360, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2631, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2644, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2649, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2651, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2654, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2665, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2669, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2672, 2360, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2682, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2687, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2692, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2695, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2705, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2707, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2712, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2717, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2728, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2730, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2734, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2758, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2780, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2787, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2802, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2809, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2822, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2831, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2854, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2875, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2898, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2918, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2936, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2944, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 2959, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2976, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 2985, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3003, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3009, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3027, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3034, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3050, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3069, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3094, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3119, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3144, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3169, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3180, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3204, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3232, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3292, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3340, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3369, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3399, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3429, 2380, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3464, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3489, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3512, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3551, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3582, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3611, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3639, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3729, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 3817, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 3942, 2360, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 4049, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4134, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 4194, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4353, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4449, 2360, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 4562, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4672, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4769, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4849, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 4889, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4929, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 4969, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5009, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5049, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5092, 2360, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5209, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 5298, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 5468, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 5582, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5702, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 5888, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 6092, 2340, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 6240, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 6609, 2340, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 6752, 2380, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 6930, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 7000, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP },
{ 7070, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 7251, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
{ 0, 0, false, 0 },
};
// clang-format on
#endif
#endif /*__TUNE_CONFIG_H__*/

30
firmware/common/tuning.c
View File

@@ -143,7 +143,10 @@ bool set_freq(const uint64_t freq)
#else
bool tuning_set_frequency(const tune_config_t* cfg, const uint64_t freq)
bool tuning_set_frequency(
const tune_config_t* cfg,
const uint64_t freq,
const uint32_t offset)
{
uint64_t mixer_freq_hz;
uint64_t real_mixer_freq_hz;
@@ -154,31 +157,42 @@ bool tuning_set_frequency(const tune_config_t* cfg, const uint64_t freq)
const uint16_t freq_mhz = freq / FREQ_ONE_MHZ;
uint64_t rf = freq;
if (cfg->shift == FPGA_QUARTER_SHIFT_MODE_DOWN) {
if (offset > rf) {
rf = offset - rf;
} else {
rf = rf - offset;
}
} else if (cfg->shift == FPGA_QUARTER_SHIFT_MODE_UP) {
rf = rf + offset;
}
max2831_mode_t prior_max2831_mode = max2831_mode(&max283x);
max2831_set_mode(&max283x, MAX2831_MODE_STANDBY);
if (cfg->if_mhz == 0) {
rf_path_set_filter(&rf_path, RF_PATH_FILTER_BYPASS);
max2831_set_frequency(&max283x, freq);
max2831_set_frequency(&max283x, rf);
sgpio_cpld_set_mixer_invert(&sgpio_config, 0);
} else if (cfg->if_mhz > freq_mhz) {
rf_path_set_filter(&rf_path, RF_PATH_FILTER_LOW_PASS);
if (cfg->high_lo) {
mixer_freq_hz = FREQ_ONE_MHZ * cfg->if_mhz + freq;
mixer_freq_hz = FREQ_ONE_MHZ * cfg->if_mhz + rf;
real_mixer_freq_hz = mixer_set_frequency(&mixer, mixer_freq_hz);
max2831_set_frequency(&max283x, real_mixer_freq_hz - freq);
max2831_set_frequency(&max283x, real_mixer_freq_hz - rf);
sgpio_cpld_set_mixer_invert(&sgpio_config, 1);
} else {
mixer_freq_hz = FREQ_ONE_MHZ * cfg->if_mhz - freq;
mixer_freq_hz = FREQ_ONE_MHZ * cfg->if_mhz - rf;
real_mixer_freq_hz = mixer_set_frequency(&mixer, mixer_freq_hz);
max2831_set_frequency(&max283x, real_mixer_freq_hz + freq);
max2831_set_frequency(&max283x, real_mixer_freq_hz + rf);
sgpio_cpld_set_mixer_invert(&sgpio_config, 0);
}
} else {
rf_path_set_filter(&rf_path, RF_PATH_FILTER_HIGH_PASS);
mixer_freq_hz = freq - FREQ_ONE_MHZ * cfg->if_mhz;
mixer_freq_hz = rf - FREQ_ONE_MHZ * cfg->if_mhz;
real_mixer_freq_hz = mixer_set_frequency(&mixer, mixer_freq_hz);
max2831_set_frequency(&max283x, freq - real_mixer_freq_hz);
max2831_set_frequency(&max283x, rf - real_mixer_freq_hz);
sgpio_cpld_set_mixer_invert(&sgpio_config, 0);
}

5
firmware/common/tuning.h
View File

@@ -39,7 +39,10 @@ bool set_freq_explicit(
const rf_path_filter_t path);
#ifdef PRALINE
bool tuning_set_frequency(const tune_config_t* config, const uint64_t frequency_hz);
bool tuning_set_frequency(
const tune_config_t* cfg,
const uint64_t freq,
const uint32_t offset);
#endif
#endif /*__TUNING_H__*/