mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-03-06 23:39:56 +01:00
Add FPGA SPI test
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@@ -137,6 +137,31 @@ static int rx_samples(const unsigned int num_samples, uint32_t max_cycles)
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return rc;
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}
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bool fpga_spi_selftest()
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{
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// Skip if FPGA configuration failed.
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if (selftest.fpga_image_load != PASSED) {
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selftest.fpga_spi = SKIPPED;
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return false;
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}
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// Test writing a register and reading it back.
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uint8_t reg = 5;
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uint8_t write_value = 0xA5;
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ssp1_set_mode_ice40();
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ice40_spi_write(&ice40, reg, write_value);
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uint8_t read_value = ice40_spi_read(&ice40, reg);
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ssp1_set_mode_max283x();
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// Update selftest result.
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selftest.fpga_spi = (read_value == write_value) ? PASSED : FAILED;
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if (selftest.fpga_spi != PASSED) {
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selftest.report.pass = false;
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}
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return selftest.fpga_spi == PASSED;
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}
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static uint8_t lfsr_advance(uint8_t v)
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{
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const uint8_t feedback = ((v >> 3) ^ (v >> 4) ^ (v >> 5) ^ (v >> 7)) & 1;
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@@ -145,15 +170,10 @@ static uint8_t lfsr_advance(uint8_t v)
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bool fpga_sgpio_selftest()
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{
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#if defined(DFU_MODE) || defined(RAM_MODE)
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selftest.sgpio_rx = SKIPPED;
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return false;
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#endif
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bool timeout = false;
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// Skip if FPGA configuration failed.
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if (selftest.fpga_image_load != PASSED) {
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// Skip if FPGA configuration failed or its SPI bus is not working.
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if ((selftest.fpga_image_load != PASSED) || (selftest.fpga_spi != PASSED)) {
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selftest.sgpio_rx = SKIPPED;
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return false;
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}
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@@ -241,15 +261,10 @@ static bool in_range(int value, int expected, int error)
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bool fpga_if_xcvr_selftest()
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{
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#if defined(DFU_MODE) || defined(RAM_MODE)
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selftest.xcvr_loopback = SKIPPED;
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return false;
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#endif
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bool timeout = false;
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// Skip if FPGA configuration failed.
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if (selftest.fpga_image_load != PASSED) {
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// Skip if FPGA configuration failed or its SPI bus is not working.
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if ((selftest.fpga_image_load != PASSED) || (selftest.fpga_spi != PASSED)) {
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selftest.xcvr_loopback = SKIPPED;
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return false;
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}
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@@ -25,6 +25,7 @@
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#include <stdbool.h>
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bool fpga_image_load(unsigned int index);
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bool fpga_spi_selftest();
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bool fpga_sgpio_selftest();
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bool fpga_if_xcvr_selftest();
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@@ -51,6 +51,7 @@ typedef struct {
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bool si5351_readback_ok;
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#ifdef PRALINE
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test_result_t fpga_image_load;
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test_result_t fpga_spi;
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test_result_t sgpio_rx;
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test_result_t xcvr_loopback;
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@@ -290,6 +290,7 @@ int main(void)
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#else
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fpga_image_load(0);
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delay_us_at_mhz(100, 204);
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fpga_spi_selftest();
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fpga_sgpio_selftest();
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#endif
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@@ -116,6 +116,9 @@ void generate_selftest_report(void)
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append(&s, &c, "FPGA configuration: ");
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append(&s, &c, test_result_to_str(selftest.fpga_image_load));
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append(&s, &c, "\n");
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append(&s, &c, "FPGA SPI: ");
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append(&s, &c, test_result_to_str(selftest.fpga_spi));
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append(&s, &c, "\n");
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append(&s, &c, "SGPIO RX test: ");
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append(&s, &c, test_result_to_str(selftest.sgpio_rx));
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append(&s, &c, "\n");
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