/*
 * This file is part of the Trezor project, https://trezor.io/
 *
 * Copyright (c) SatoshiLabs
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.p
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#pragma once

// I2C address of the DRV262X on the I2C bus.
#define DRV262X_I2C_ADDRESS 0x5A

// ------------------------------------------------------------
// DRV262X registers
// ------------------------------------------------------------

// Register 0x00
#define DRV262X_R0 0x00
#define DRV262X_R0_CHIPID_POS 4
#define DRV262X_R0_CHIPID_MASK 0xF << DRV2625_R0_CHIPID_POS
#define DRV262X_R0_REV_POS 0
#define DRV262X_R0_REV_MASK 0xF << DRV2625_R0_REV_POS

// Register 0x01
#define DRV262X_R1 0x01
#define DRV262X_R1_OC_DETECT_POS 0
#define DRV262X_R1_OC_DETECT_MASK 0x1 << DRV2625_R1_OC_DETECT_POS
#define DRV262X_R1_OVER_TEMP_POS 1
#define DRV262X_R1_OVER_TEMP_MASK 0x1 << DRV2625_R1_OVER_TEMP_POS
#define DRV262X_R1_UVLO_POS 2
#define DRV262X_R1_UVLO_MASK 0x1 << DRV2625_R1_UVLO_POS
#define DRV262X_R1_PROCESS_DONE_POS 3
#define DRV262X_R1_PROCESS_DONE_MASK 0x1 << DRV2625_R1_PROCESS_DONE_POS
#define DRV262X_R1_PROG_ERROR_POS 4
#define DRV262X_R1_PROG_ERROR_MASK 0x1 << DRV2625_R1_PROG_ERROR_POS
#define DRV262X_R1_DIAG_RESULT_POS 7
#define DRV262X_R1_DIAG_RESULT_MASK 0x1 << DRV2625_R1_DIAG_RESULT_POS

// Register 0x02
#define DRV262X_R2 0x02
#define DRV262X_R2_INTZ_POS 0
#define DRV262X_R2_INTZ_MASK 0x1 << DRV262X_R2_INTZ_POS

// Register 0x03
#define DRV262X_R3 0x03
#define DRV262X_R3_DIAG_RESULT_POS 0
#define DRV262X_R3_DIAG_RESULT_MASK 0xFF << DRV262X_R3_DIAG_RESULT_POS

// Register 0x04
#define DRV262X_R4 0x04
#define DRV262X_R4_VBAT_POS 0
#define DRV262X_R4_VBAT_MASK 0xFF << DRV262X_R4_VBAT_POS

// Register 0x05
#define DRV262X_R5_LRA_PERIOD 0x05
#define DRV262X_R5_LRA_PERIOD_MSB_POS 0
#define DRV262X_R5_LRA_PERIOD_MSB_MASK 0x3 << DRV262X_LRA_PERIOD_MSB_POS

// Register 0x06
#define DRV262X_R6_LRA_PERIOD_LSB 0x06
#define DRV262X_R6_LRA_PERIOD_LSB_POS 0
#define DRV262X_R6_LRA_PERIOD_LSB_MASK 0xFF << DRV262X_LRA_PERIOD_LSB_POS

// Register 0x7
#define DRV262X_R7 0x07
#define DRV262X_R7_MODE_POS 0
#define DRV262X_R7_MODE_MASK 0x3 << DRV262X_R7_MODE_POS
#define DRV262X_R7_TRIG_PIN_FUNC_POS 2
#define DRV262X_R7_TRIG_PIN_FUNC_MASK 0x3 << DRV262X_R7_TRIG_PIN_FUNC_POS
#define DRV262X_R7_LINEREF_COMP_SEL_POS 4
#define DRV262X_R7_LINEREF_COMP_SEL_MASK 0x3 << DRV262X_R7_LINEREF_COMP_SEL_POS
#define DRV262X_R7_LRA_PERIOD_AVG_DIS_POS 6
#define DRV262X_R7_LRA_PERIOD_AVG_DIS_MASK \
  0x1 << DRV262X_R7_LRA_PERIOD_AVG_DIS_POS
#define DRV262X_R7_I2C_BCAST_EN_POS 7
#define DRV262X_R7_I2C_BCAST_EN_MASK 0x1 << DRV262X_R7_I2C_BCAST_EN_POS

// MODE configurations
#define DRV262X_R7_MODE_RTP 0x0
#define DRV262X_R7_MODE_WAVEFORM 0x1
#define DRV262X_R7_MODE_DIAG 0x2
#define DRV262X_R7_MODE_AUTOCAL 0x3

// Trig Pin Func configurations
#define DRV262X_R7_TRIG_PIN_FUNC_PULSE 0x0
#define DRV262X_R7_TRIG_PIN_FUNC_EXT_TRIG 0x1
#define DRV262X_R7_TRIG_PIN_FUNC_INT 0x2

// Register 0x08
#define DRV262X_R8 0x8
#define DRV262X_R8_INPUT_SLOPE_CHECK_POS 2
#define DRV262X_R8_INPUT_SLOPE_CHECK_MASK \
  0x1 << DRV262X_R8_INPUT_SLOPE_CHECK_POS
#define DRV262X_R8_AUTO_BRK_INT_O_STBY_POS 3
#define DRV262X_R8_AUTO_BRK_INT_O_STBY_MASK \
  0x1 << DRV262X_R8_AUTO_BRK_INT_O_STBY_POS
#define DRV262X_R8_AUTO_BRK_OL_POS 4
#define DRV262X_R8_AUTO_BRK_OL_MASK 0x1 << DRV262X_R8_AUTO_BRK_OL_POS
#define DRV262X_R8_HYBRID_LOOP_POS 5
#define DRV262X_R8_HYBRID_LOOP_MASK 0x1 << DRV262X_R8_HYBRID_LOOP_POS
#define DRV262X_R8_CONTROL_LOOP_POS 6
#define DRV262X_R8_CONTROL_LOOP_MASK 0x1 << DRV262X_R8_CONTROL_LOOP_POS
#define DRV262X_R8_LRA_ERM_POS 7
#define DRV262X_R8_LRA_ERM_MASK 0x1 << DRV262X_R8_LRA_ERM_POS

// Register 0x09
#define DRV262X_R9 0x09
#define DRV262X_R9_UVLO_THRES_POS 0
#define DRV262X_R9_UVLO_THRES_MASK 0x3 << DRV262X_R9_UVLO_THRES_POS
#define DRV262X_R9_BAT_LIFE_EXT_LVL_EN_POS 2
#define DRV262X_R9_BAT_LIFE_EXT_LVL_EN_MASK \
  0x1 << DRV262X_R9_BAT_LIFE_EXT_LVL_EN_POS

// Register 0x0A
#define DRV262X_RA 0x0A
#define DRV262X_RA_BAT_LIFE_EXT_LVL1_POS 0
#define DRV262X_RA_BAT_LIFE_EXT_LVL1_MASK \
  0xFF << DRV262X_RA_BAT_LIFE_EXT_LVL1_POS

// Register 0x0B
#define DRV262X_RB 0x0B
#define DRV262X_RB_BAT_LIFE_EXT_LVL2_POS 0
#define DRV262X_RB_BAT_LIFE_EXT_LVL2_MASK \
  0xFF << DRV262X_RB_BAT_LIFE_EXT_LVL2_POS

// Register 0x0C
#define DRV262X_RC 0x0C
#define DRV262X_RC_GO_POS 0
#define DRV262X_RC_GO_MASK 0x1 << DRV262X_RC_GO_POS

// Register 0x0D
#define DRV262X_RD 0x0D
#define DRV262X_RD_DIAG_MEM_GAIN_POS 0
#define DRV262X_RD_DIAG_MEM_GAIN_MASK 0x3 << DRV262X_RD_DIAG_MEM_GAIN_POS
#define DRV262X_RD_PLAYBACK_INTERVAL_POS 5
#define DRV262X_RD_PLAYBACK_INTERVAL_MASK \
  0x3 << DRV262X_RD_PLAYBACK_INTERVAL_POS
#define DRV262X_RD_LIB_SEL_POS 6
#define DRV262X_RD_LIB_SEL_MASK 0x1 << DRV262X_RD_LIB_SEL_POS
#define DRV262X_RD_LIB_ENABLE_POS 7
#define DRV262X_RD_LIB_ENABLE_MASK 0x1 << DRV262X_RD_LIB_ENABLE_POS

// Register 0x0E
#define DRV262X_RE 0x0E
#define DRV262X_REG_RTP_POS 0
#define DRV262X_REG_RTP_MASK 0xFF << DRV262X_REG_RTP_POS

// Register 0x0F
#define DRV262X_RF 0x0F
#define DRV262X_RF_WAV_FRM_SEQ1_POS 0
#define DRV262X_RF_WAV_FRM_SEQ1_MASK 0x7F << DRV262X_RF_WAV_FRM_SEQ1_POS
#define DRV262X_RF_WAIT1_POS 7
#define DRV262X_RF_WAIT1_MASK 0x1 << DRV262X_RF_WAIT1_POS

// Register 0x10
#define DRV262X_R10 0x10
#define DRV262X_R10_WAV_FRM_SEQ2_POS 0
#define DRV262X_R10_WAV_FRM_SEQ2_MASK 0x7F << DRV262X_R10_WAV_FRM_SEQ2_POS
#define DRV262X_R10_WAIT2_POS 7
#define DRV262X_R10_WAIT2_MASK 0x1 << DRV262X_R10_WAIT2_POS

// Register 0x11
#define DRV262X_R11 0x11
#define DRV262X_R11_WAV_FRM_SEQ3_POS 0
#define DRV262X_R11_WAV_FRM_SEQ3_MASK 0x7F << DRV262X_R11_WAV_FRM_SEQ3_POS
#define DRV262X_R11_WAIT3_POS 7
#define DRV262X_R11_WAIT3_MASK 0x1 << DRV262X_R11_WAIT3_POS

// Register 0x12
#define DRV262X_R12 0x12
#define DRV262X_R12_WAV_FRM_SEQ4_POS 0
#define DRV262X_R12_WAV_FRM_SEQ4_MASK 0x7F << DRV262X_R12_WAV_FRM_SEQ4_POS
#define DRV262X_R12_WAIT4_POS 7
#define DRV262X_R12_WAIT4_MASK 0x1 << DRV262X_R12_WAIT4_POS

// Register 0x13
#define DRV262X_R13 0x13
#define DRV262X_R13_WAV_FRM_SEQ5_POS 0
#define DRV262X_R13_WAV_FRM_SEQ5_MASK 0x7F << DRV262X_R13_WAV_FRM_SEQ5_POS
#define DRV262X_R13_WAIT5_POS 7
#define DRV262X_R13_WAIT5_MASK 0x1 << DRV262X_R13_WAIT5_POS

// Register 0x14
#define DRV262X_R14 0x14
#define DRV262X_R14_WAV_FRM_SEQ6_POS 0
#define DRV262X_R14_WAV_FRM_SEQ6_MASK 0x7F << DRV262X_R14_WAV_FRM_SEQ6_POS
#define DRV262X_R14_WAIT6_POS 7
#define DRV262X_R14_WAIT6_MASK 0x1 << DRV262X_R14_WAIT6_POS

// Register 0x15
#define DRV262X_R15 0x15
#define DRV262X_R15_WAV_FRM_SEQ7_POS 0
#define DRV262X_R15_WAV_FRM_SEQ7_MASK 0x7F << DRV262X_R15_WAV_FRM_SEQ7_POS
#define DRV262X_R15_WAIT7_POS 7
#define DRV262X_R15_WAIT7_MASK 0x1 << DRV262X_R15_WAIT7_POS

// Register 0x16
#define DRV262X_R16 0x16
#define DRV262X_R16_WAV_FRM_SEQ8_POS 0
#define DRV262X_R16_WAV_FRM_SEQ8_MASK 0x7F << DRV262X_R16_WAV_FRM_SEQ8_POS
#define DRV262X_R16_WAIT8_POS 7
#define DRV262X_R16_WAIT8_MASK 0x1 << DRV262X_R16_WAIT8_POS

// Register 0x17
#define DRV262X_R17 0x17
#define DRV262X_R17_WAW1_SEQ_LOOP_POS 0
#define DRV262X_R17_WAW1_SEQ_LOOP_MASK 0x3 << DRV262X_R17_WAW1_SEQ_LOOP_POS
#define DRV262X_R17_WAW2_SEQ_LOOP_POS 2
#define DRV262X_R17_WAW2_SEQ_LOOP_MASK 0x3 << DRV262X_R17_WAW2_SEQ_LOOP_POS
#define DRV262X_R17_WAW3_SEQ_LOOP_POS 4
#define DRV262X_R17_WAW3_SEQ_LOOP_MASK 0x3 << DRV262X_R17_WAW3_SEQ_LOOP_POS
#define DRV262X_R17_WAW4_SEQ_LOOP_POS 6
#define DRV262X_R17_WAW4_SEQ_LOOP_MASK 0x3 << DRV262X_R17_WAW4_SEQ_LOOP_POS

// Register 0x18
#define DRV262X_R18 0x18
#define DRV262X_R18_WAW5_SEQ_LOOP_POS 0
#define DRV262X_R18_WAW5_SEQ_LOOP_MASK 0x3 << DRV262X_R18_WAW5_SEQ_LOOP_POS
#define DRV262X_R18_WAW6_SEQ_LOOP_POS 2
#define DRV262X_R18_WAW6_SEQ_LOOP_MASK 0x3 << DRV262X_R18_WAW6_SEQ_LOOP_POS
#define DRV262X_R18_WAW7_SEQ_LOOP_POS 4
#define DRV262X_R18_WAW7_SEQ_LOOP_MASK 0x3 << DRV262X_R18_WAW7_SEQ_LOOP_POS
#define DRV262X_R18_WAW8_SEQ_LOOP_POS 6
#define DRV262X_R18_WAW8_SEQ_LOOP_MASK 0x3 << DRV262X_R18_WAW8_SEQ_LOOP_POS

// Register 0x19
#define DRV262X_R19 0x19
#define DRV262X_R19_WAW_SEQ_MAIN_LOOP_POS 0
#define DRV262X_R19_WAW_SEQ_MAIN_LOOP_MASK \
  0x7 << DRV262X_R19_WAW_SEQ_MAIN_LOOP_POS

// Register 0x1A
#define DRV262X_R1A 0x1A
#define DRV262X_R1A_ODT_POS 0
#define DRV262X_R1A_ODT_MASK 0xFF << DRV262X_R1A_ODT_POS

// Register 0x1B
#define DRV262X_R1B 0x1B
#define DRV262X_R1B_SPT_POS 0
#define DRV262X_R1B_SPT_MASK 0xFF << DRV262X_R1B_SPT_POS

// Register 0x1C
#define DRV262X_R1C 0x1C
#define DRV262X_R1C_SNT_POS 0
#define DRV262X_R1C_SNT_MASK 0xFF << DRV262X_R1C_SNT_POS

// Register 0x1D
#define DRV262X_R1D 0x1D
#define DRV262X_R1D_BRT_POS 0
#define DRV262X_R1D_BRT_MASK 0xFF << DRV262X_R1D_BRT_POS

// Register 0x1F
#define DRV262X_R1F 0x1F
#define DRV262X_R1F_RATED_VOLTAGE_POS 0
#define DRV262X_R1F_RATED_VOLTAGE_MASK 0xFF << DRV262X_R1F_RATED_VOLTAGE_POS

// Register 0x20
#define DRV262X_R20 0x20
#define DRV262X_R20_OD_CLAMP_POS 0
#define DRV262X_R20_OD_CLAMP_MASK 0xFF << DRV262X_R20_OD_CLAMP_POS

// Register 0x21
#define DRV262X_R21 0x21
#define DRV262X_R21_A_CAL_COMP_POS 0
#define DRV262X_R21_A_CAL_COMP_MASK 0xFF << DRV262X_R21_A_CAL_COMP_POS

// Register 0x22
#define DRV262X_R22 0x22
#define DRV262X_R22_A_CAL_BEMF_POS 0
#define DRV262X_R22_A_CAL_BEMF_MASK 0xFF << DRV262X_R22_A_CAL_BEMF_POS

// Register 0x23
#define DRV262X_R23 0x23
#define DRV262X_R23_BEMF_GAIN_POS 0
#define DRV262X_R23_BEMF_GAIN_MASK 0x3 << DRV262X_R23_BEMF_GAIN_POS
#define DRV262X_R23_LOOP_GAIN_POS 2
#define DRV262X_R23_LOOP_GAIN_MASK 0x3 << DRV262X_R23_LOOP_GAIN_POS
#define DRV262X_R23_FB_BREAK_FACTOR_POS 4
#define DRV262X_R23_FB_BREAK_FACTOR_MASK 0x7 << DRV262X_R23_FB_BREAK_FACTOR_POS
#define DRV262X_R23_NG_THRESH_POS 7
#define DRV262X_R23_NG_THRESH_MASK 0x1 << DRV262X_R23_NG_THRESH_POS

// Register 0x24
#define DRV262X_R24 0x24
#define DRV262X_R24_RATED_VOLTAGE_CLAMP_POS 0
#define DRV262X_R24_RATED_VOLTAGE_CLAMP_MASK \
  0xFF << DRV262X_R24_RATED_VOLTAGE_CLAMP_POS

// Register 0x25
#define DRV262X_R25 0x25
#define DRV262X_R25_OD_CLAMP_LVL1_POS 0
#define DRV262X_R25_OD_CLAMP_LVL1_MASK 0xFF << DRV262X_R25_OD_CLAMP_LVL1_POS

// Register 0x26
#define DRV262X_R26 0x26
#define DRV262X_R26_OD_CLAMP_LVL2_POS 0
#define DRV262X_R26_OD_CLAMP_LVL2_MASK 0xFF << DRV262X_R26_OD_CLAMP_LVL2_POS

// Register 0x27
#define DRV262X_R27 0x27
#define DRV262X_R27_DRIVE_TIME_POS 0
#define DRV262X_R27_DRIVE_TIME_MASK 0x1F << DRV262X_R27_DRIVE_TIME_POS

// Register 0x28
#define DRV262X_R28 0x28
#define DRV262X_R28_IDISS_TIME_POS 0
#define DRV262X_R28_IDISS_TIME_MASK 0x0F << DRV262X_R28_IDISS_TIME_POS
#define DRV262X_R28_BLANK_TIME_POS 4
#define DRV262X_R28_BLANK_TIME_MASK 0x0F << DRV262X_R28_BLANK_TIME_POS

// Register 0x29
#define DRV262X_R29 0x29
#define DRV262X_R29_ZC_DET_TIME_POS 0
#define DRV262X_R29_ZC_DET_TIME_MASK 0x3 << DRV262X_R29_ZC_DET_TIME_POS
#define DRV262X_R29_SAMPLE_TIME_POS 2
#define DRV262X_R29_SAMPLE_TIME_MASK 0x3 << DRV262X_R29_SAMPLE_TIME_POS
#define DRV262X_R29_OC_CLAMP_TIME_POS 4
#define DRV262X_R29_OC_CLAMP_TIME_MASK 0x3 << DRV262X_R29_OC_CLAMP_TIME_POS

// Register 0x2A
#define DRV262X_R2A 0x2A
#define DRV262X_R2A_AUTO_CAL_TIME_POS 0
#define DRV262X_R2A_AUTO_CAL_TIME_MASK 0x3 << DRV262X_R2A_AUTO_CAL_TIME_POS

// Register 0x2C
#define DRV262X_R2C 0x2C
#define DRV262X_R2C_LRA_WAVE_SHAPE_POS 0
#define DRV262X_R2C_LRA_WAVE_SHAPE_MASK 0x1 << DRV262X_R2C_LRA_WAVE_SHAPE_POS
#define DRV262X_R2C_AUTO_OL_CNT_POS 5
#define DRV262X_R2C_AUTO_OL_CNT_MASK 0x3 << DRV262X_R2C_AUTO_OL_CNT_POS
#define DRV262X_R2C_LRA_AUTO_OPEN_LOOP_POS 7
#define DRV262X_R2C_LRA_AUTO_OPEN_LOOP_MASK \
  0x1 << DRV262X_R2C_LRA_AUTO_OPEN_LOOP_POS

// Register 0x2E
#define DRV262X_R2E 0x2E
#define DRV262X_R2E_OL_LRA_PERIOD_HI_POS 0x2E
#define DRV262X_R2E_OL_LRA_PERIOD_HI_MASK \
  0x03 << DRV262X_R2E_OL_LRA_PERIOD_HI_POS

// Register 0x2F
#define DRV262X_R2F 0x2F
#define DRV262X_R2F_OL_LRA_PERIOD_LO_POS 0
#define DRV262X_R2F_OL_LRA_PERIOD_LO_MASK \
  0xFF << DRV262X_R2F_OL_LRA_PERIOD_LO_POS

// Register 0x30
#define DRV262X_R30 0x30
#define DRV262X_R30_CURRENT_K_POS 0
#define DRV262X_R30_CURRENT_K_MASK 0xFF << DRV262X_R30_CURRENT_K_POS

#ifdef HAPTIC_CHIP_DRV2624

// DRV2624 RAM register address definitions
#define DRV2624_RAM_ADDR_H 0xFD
#define DRV2624_RAM_ADDR_L 0xFE
#define DRV2624_RAM_DATA 0xFF

#endif

// ------------------------------------------------------------
// DRV2625 effect types
// ------------------------------------------------------------

typedef enum {
  STRONG_CLICK_100 = 1,
  STRONG_CLICK_60 = 2,
  STRONG_CLICK_30 = 3,
  SHARP_CLICK_100 = 4,
  SHARP_CLICK_60 = 5,
  SHARP_CLICK_30 = 6,
  SOFT_BUMP_100 = 7,
  SOFT_BUMP_60 = 8,
  SOFT_BUMP_30 = 9,
  DOUBLE_CLICK_100 = 10,
  DOUBLE_CLICK_60 = 11,
  TRIPLE_CLICK_100 = 12,
  SOFT_FUZZ_60 = 13,
  STRONG_BUZZ_100 = 14,
  ALERT_750MS_100 = 15,
  ALERT_1000MS_100 = 16,
  STRONG_CLICK_1_100 = 17,
  STRONG_CLICK_2_80 = 18,
  STRONG_CLICK_3_60 = 19,
  STRONG_CLICK_4_30 = 20,
  MEDIUM_CLICK_1_100 = 21,
  MEDIUM_CLICK_2_80 = 22,
  MEDIUM_CLICK_3_60 = 23,
  SHARP_TICK_1_100 = 24,
  SHARP_TICK_2_80 = 25,
  SHARP_TICK_3_60 = 26,
  SHORT_DOUBLE_CLICK_STRONG_1_100 = 27,
  SHORT_DOUBLE_CLICK_STRONG_2_80 = 28,
  SHORT_DOUBLE_CLICK_STRONG_3_60 = 29,
  SHORT_DOUBLE_CLICK_STRONG_4_30 = 30,
  SHORT_DOUBLE_CLICK_MEDIUM_1_100 = 31,
  SHORT_DOUBLE_CLICK_MEDIUM_2_80 = 32,
  SHORT_DOUBLE_CLICK_MEDIUM_3_60 = 33,
  SHORT_DOUBLE_SHARP_TICK_1_100 = 34,
  SHORT_DOUBLE_SHARP_TICK_2_80 = 35,
  SHORT_DOUBLE_SHARP_TICK_3_60 = 36,
  LONG_DOUBLE_SHARP_TICK_STRONG_1_100 = 37,
  LONG_DOUBLE_SHARP_TICK_STRONG_2_80 = 38,
  LONG_DOUBLE_SHARP_TICK_STRONG_3_60 = 39,
  LONG_DOUBLE_SHARP_TICK_STRONG_4_30 = 40,
  LONG_DOUBLE_SHARP_TICK_MEDIUM_1_100 = 41,
  LONG_DOUBLE_SHARP_TICK_MEDIUM_2_80 = 42,
  LONG_DOUBLE_SHARP_TICK_MEDIUM_3_60 = 43,
  LONG_DOUBLE_SHARP_TICK_1_100 = 44,
  LONG_DOUBLE_SHARP_TICK_2_80 = 45,
  LONG_DOUBLE_SHARP_TICK_3_60 = 46,
  BUZZ_1_100 = 47,
  BUZZ_2_80 = 48,
  BUZZ_3_60 = 49,
  BUZZ_4_40 = 50,
  BUZZ_5_20 = 51,
  PULSING_STRONG_1_100 = 52,
  PULSING_STRONG_2_60 = 53,
  PULSING_MEDIUM_1_100 = 54,
  PULSING_MEDIUM_2_60 = 55,
  PULSING_SHARP_1_100 = 56,
  PULSING_SHARP_2_60 = 57,
  TRANSITION_CLICK_1_100 = 58,
  TRANSITION_CLICK_2_80 = 59,
  TRANSITION_CLICK_3_60 = 60,
  TRANSITION_CLICK_4_40 = 61,
  TRANSITION_CLICK_5_20 = 62,
  TRANSITION_CLICK_6_10 = 63,
  TRANSITION_HUM_1_100 = 64,
  TRANSITION_HUM_2_80 = 65,
  TRANSITION_HUM_3_60 = 66,
  TRANSITION_HUM_4_40 = 67,
  TRANSITION_HUM_5_20 = 68,
  TRANSITION_HUM_6_10 = 69,
  TRANSITION_RAMP_DOWN_LONG_SMOOTH_1 = 70,
  TRANSITION_RAMP_DOWN_LONG_SMOOTH_2 = 71,
  TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1 = 72,
  TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2 = 73,
  TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1 = 74,
  TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2 = 75,
  TRANSITION_RAMP_DOWN_LONG_SHARP_1 = 76,
  TRANSITION_RAMP_DOWN_LONG_SHARP_2 = 77,
  TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1 = 78,
  TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2 = 79,
  TRANSITION_RAMP_DOWN_SHORT_SHARP_1 = 80,
  TRANSITION_RAMP_DOWN_SHORT_SHARP_2 = 81,
  TRANSITION_RAMP_UP_LONG_SMOOTH_1 = 82,
  TRANSITION_RAMP_UP_LONG_SMOOTH_2 = 83,
  TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1 = 84,
  TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2 = 85,
  TRANSITION_RAMP_UP_SHORT_SMOOTH_1 = 86,
  TRANSITION_RAMP_UP_SHORT_SMOOTH_2 = 87,
  TRANSITION_RAMP_UP_LONG_SHARP_1 = 88,
  TRANSITION_RAMP_UP_LONG_SHARP_2 = 89,
  TRANSITION_RAMP_UP_MEDIUM_SHARP_1 = 90,
  TRANSITION_RAMP_UP_MEDIUM_SHARP_2 = 91,
  TRANSITION_RAMP_UP_SHORT_SHARP_1 = 92,
  TRANSITION_RAMP_UP_SHORT_SHARP_2 = 93,
  TRANSITION_RAMP_DOWN_LONG_SMOOTH_1_50 = 94,
  TRANSITION_RAMP_DOWN_LONG_SMOOTH_2_50 = 95,
  TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_1_50 = 96,
  TRANSITION_RAMP_DOWN_MEDIUM_SMOOTH_2_50 = 97,
  TRANSITION_RAMP_DOWN_SHORT_SMOOTH_1_50 = 98,
  TRANSITION_RAMP_DOWN_SHORT_SMOOTH_2_50 = 99,
  TRANSITION_RAMP_DOWN_LONG_SHARP_1_50 = 100,
  TRANSITION_RAMP_DOWN_LONG_SHARP_2_50 = 101,
  TRANSITION_RAMP_DOWN_MEDIUM_SHARP_1_50 = 102,
  TRANSITION_RAMP_DOWN_MEDIUM_SHARP_2_50 = 103,
  TRANSITION_RAMP_DOWN_SHORT_SHARP_1_50 = 104,
  TRANSITION_RAMP_DOWN_SHORT_SHARP_2_50 = 105,
  TRANSITION_RAMP_UP_LONG_SMOOTH_1_50 = 106,
  TRANSITION_RAMP_UP_LONG_SMOOTH_2_50 = 107,
  TRANSITION_RAMP_UP_MEDIUM_SMOOTH_1_50 = 108,
  TRANSITION_RAMP_UP_MEDIUM_SMOOTH_2_50 = 109,
  TRANSITION_RAMP_UP_SHORT_SMOOTH_1_50 = 110,
  TRANSITION_RAMP_UP_SHORT_SMOOTH_2_50 = 111,
  TRANSITION_RAMP_UP_LONG_SHARP_1_50 = 112,
  TRANSITION_RAMP_UP_LONG_SHARP_2_50 = 113,
  TRANSITION_RAMP_UP_MEDIUM_SHARP_1_50 = 114,
  TRANSITION_RAMP_UP_MEDIUM_SHARP_2_50 = 115,
  TRANSITION_RAMP_UP_SHORT_SHARP_1_50 = 116,
  TRANSITION_RAMP_UP_SHORT_SHARP_2_50 = 117,
  LONG_BUZZ_FROM_PROGRAMMATIC_STOPPING = 118,
  SMOOTH_HUM_1_100 = 119,
  SMOOTH_HUM_2_80 = 120,
  SMOOTH_HUM_3_60 = 121,
  SMOOTH_HUM_4_40 = 122,
  SMOOTH_HUM_5_20 = 123,
} drv2625_lib_effect_t;
