From d54cb4fa96dd836a17ad8ecc71cb9099c8e7678e Mon Sep 17 00:00:00 2001 From: mossmann Date: Mon, 30 Apr 2012 22:35:39 -0700 Subject: [PATCH] Updated Clocking (markdown) --- Clocking.md | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/Clocking.md b/Clocking.md index 609850e..bf8f8be 100644 --- a/Clocking.md +++ b/Clocking.md @@ -4,8 +4,17 @@ HackRF clock signals are generated by the Si5351. The plan so far: * optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division) * VCO frequency: 800 MHz (supports 600 to 900 MHz) * MAX2837 clock: 40 MHz -* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz -* A DDR clock at double the MAX5864 will be delivered to the CPLD. -* LPC43xx clock: 20 MHz (from integer-only output) +* preferred MAX5864 clocks: 8, 10, 12.5, 20 MHz +* A clock at quadruple the MAX5864 rate will be delivered to the CPLD. +* LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work) -The LPC43xx will start up on its internal RC oscillator, activate the Si5351, and then switch to the 20 MHz clock coming from the Si5351. \ No newline at end of file +Future Si5351 output mapping: + +CLK0 -> none +CLK1 -> none +CLK2 -> RFFC5071 +CLK3 -> MAX2837 +CLK4 -> MAX5864 +CLK5 -> external clock output +CLK6 -> CPLD +CLK7 -> CPLD \ No newline at end of file