hackrf

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Files

Jared Boone d103c31187 CPLD: Rework timing between ADC, CPLD, SGPIO

Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).

2019-01-18 16:09:14 -08:00

sgpio_if

CPLD: Rework timing between ADC, CPLD, SGPIO

2019-01-18 16:09:14 -08:00

README

added CPLD update requirement to firmware/README

2018-02-20 08:18:42 -07:00

README

The primary CPLD image is: sgpio_if/default.xsvf

This is a binary file built from HDL source in sgpio_if.  You do not need
Xilinx tools unless you want to make your own modifications.

To update the CPLD, first update the firmware, libhackrf, and hackrf-tools.
Then:

$ hackrf_cpldjtag -x sgpio_if/default.xsvf

After a few seconds, three LEDs should start blinking.  This indicates that the
CPLD has been programmed successfully.  Reset the HackRF device by pressing the
RESET button or by unplugging it and plugging it back in.