mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-02-20 00:33:48 +01:00
409acbc3c9
Co-authored-by: mndza <diego.hdmp@gmail.com> Co-authored-by: Martin Ling <martin-git@earth.li> Co-authored-by: Antoine van Gelder <antoine@greatscottgadgets.com>
58 lines
1.8 KiB
Python
58 lines
1.8 KiB
Python
#
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# This file is part of HackRF.
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#
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# Copyright (c) 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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# SPDX-License-Identifier: BSD-3-Clause
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from amaranth import Module, signed, Shape
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from amaranth.lib import wiring, stream, data, fifo
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from amaranth.lib.wiring import In, Out
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from ._stream import StreamSkidBuffer, StreamMux, StreamDemux
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from .lfsr import LinearFeedbackShiftRegister
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class IQSample(data.StructLayout):
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def __init__(self, width=8):
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super().__init__({
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"i": signed(width),
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"q": signed(width),
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})
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class ClockConverter(wiring.Component):
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def __init__(self, shape, depth, input_domain, output_domain, always_ready=True):
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super().__init__({
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"input": In(stream.Signature(shape, always_ready=always_ready)),
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"output": Out(stream.Signature(shape, always_ready=always_ready)),
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})
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self.shape = shape
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self.depth = depth
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self._input_domain = input_domain
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self._output_domain = output_domain
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def elaborate(self, platform):
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m = Module()
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m.submodules.mem = mem = fifo.AsyncFIFO(
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width=Shape.cast(self.shape).width,
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depth=self.depth,
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r_domain=self._output_domain,
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w_domain=self._input_domain)
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m.d.comb += [
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# write.
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mem.w_data .eq(self.input.p),
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mem.w_en .eq(self.input.valid),
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# read.
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self.output.p .eq(mem.r_data),
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self.output.valid .eq(mem.r_rdy),
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mem.r_en .eq(self.output.ready),
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]
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if not self.input.signature.always_ready:
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m.d.comb += self.input.ready.eq(mem.w_rdy)
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return m
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