mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-02-20 00:33:48 +01:00
409acbc3c9
Co-authored-by: mndza <diego.hdmp@gmail.com> Co-authored-by: Martin Ling <martin-git@earth.li> Co-authored-by: Antoine van Gelder <antoine@greatscottgadgets.com>
344 lines
10 KiB
Python
344 lines
10 KiB
Python
#
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# This file is part of HackRF.
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#
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# Copyright (c) 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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# SPDX-License-Identifier: BSD-3-Clause
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from amaranth import Module, Instance, Signal, Mux, Cat
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out
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from amaranth.vendor import SiliconBluePlatform
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class SB_MAC16(wiring.Component):
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# Input ports
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CLK: In(1)
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CE: In(1)
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C: In(16)
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A: In(16)
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B: In(16)
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D: In(16)
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AHOLD: In(1)
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BHOLD: In(1)
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CHOLD: In(1)
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DHOLD: In(1)
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IRSTTOP: In(1)
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IRSTBOT: In(1)
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ORSTTOP: In(1)
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ORSTBOT: In(1)
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OLOADTOP: In(1)
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OLOADBOT: In(1)
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ADDSUBTOP: In(1)
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ADDSUBBOT: In(1)
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OHOLDTOP: In(1)
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OHOLDBOT: In(1)
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CI: In(1)
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ACCUMCI: In(1)
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SIGNEXTIN: In(1)
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# Output ports
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O: Out(32)
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CO: Out(1)
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ACCUMCO: Out(1)
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SIGNEXTOUT: Out(1)
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def __init__(self,
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NEG_TRIGGER=0,
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C_REG=0,
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A_REG=0,
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B_REG=0,
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D_REG=0,
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TOP_8x8_MULT_REG=0,
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BOT_8x8_MULT_REG=0,
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PIPELINE_16x16_MULT_REG1=0,
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PIPELINE_16x16_MULT_REG2=0,
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TOPOUTPUT_SELECT=0,
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TOPADDSUB_LOWERINPUT=0,
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TOPADDSUB_UPPERINPUT=0,
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TOPADDSUB_CARRYSELECT=0,
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BOTOUTPUT_SELECT=0,
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BOTADDSUB_LOWERINPUT=0,
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BOTADDSUB_UPPERINPUT=0,
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BOTADDSUB_CARRYSELECT=0,
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MODE_8x8=0,
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A_SIGNED=0,
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B_SIGNED=0):
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super().__init__()
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# Parameters
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self.parameters = dict(
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NEG_TRIGGER=NEG_TRIGGER,
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C_REG=C_REG,
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A_REG=A_REG,
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B_REG=B_REG,
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D_REG=D_REG,
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TOP_8x8_MULT_REG=TOP_8x8_MULT_REG,
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BOT_8x8_MULT_REG=BOT_8x8_MULT_REG,
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PIPELINE_16x16_MULT_REG1=PIPELINE_16x16_MULT_REG1,
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PIPELINE_16x16_MULT_REG2=PIPELINE_16x16_MULT_REG2,
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TOPOUTPUT_SELECT=TOPOUTPUT_SELECT,
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TOPADDSUB_LOWERINPUT=TOPADDSUB_LOWERINPUT,
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TOPADDSUB_UPPERINPUT=TOPADDSUB_UPPERINPUT,
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TOPADDSUB_CARRYSELECT=TOPADDSUB_CARRYSELECT,
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BOTOUTPUT_SELECT=BOTOUTPUT_SELECT,
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BOTADDSUB_LOWERINPUT=BOTADDSUB_LOWERINPUT,
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BOTADDSUB_UPPERINPUT=BOTADDSUB_UPPERINPUT,
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BOTADDSUB_CARRYSELECT=BOTADDSUB_CARRYSELECT,
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MODE_8x8=MODE_8x8,
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A_SIGNED=A_SIGNED,
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B_SIGNED=B_SIGNED,
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)
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def elaborate(self, platform):
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if isinstance(platform, SiliconBluePlatform):
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return self.elaborate_hard_macro()
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else:
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return self.elaborate_simulation()
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def elaborate_hard_macro(self):
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m = Module()
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m.submodules.sb_mac16 = Instance("SB_MAC16",
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# Parameters.
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**{ f"p_{k}": v for k, v in self.parameters.items() },
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# Inputs.
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i_CLK=self.CLK,
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i_CE=self.CE,
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i_C=self.C,
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i_A=self.A,
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i_B=self.B,
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i_D=self.D,
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i_IRSTTOP=self.IRSTTOP,
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i_IRSTBOT=self.IRSTBOT,
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i_ORSTTOP=self.ORSTTOP,
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i_ORSTBOT=self.ORSTBOT,
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i_AHOLD=self.AHOLD,
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i_BHOLD=self.BHOLD,
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i_CHOLD=self.CHOLD,
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i_DHOLD=self.DHOLD,
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i_OHOLDTOP=self.OHOLDTOP,
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i_OHOLDBOT=self.OHOLDBOT,
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i_ADDSUBTOP=self.ADDSUBTOP,
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i_ADDSUBBOT=self.ADDSUBBOT,
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i_OLOADTOP=self.OLOADTOP,
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i_OLOADBOT=self.OLOADBOT,
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i_CI=self.CI,
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i_ACCUMCI=self.ACCUMCI,
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i_SIGNEXTIN=self.SIGNEXTIN,
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# Outputs.
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o_O=self.O,
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o_CO=self.CO,
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o_ACCUMCO=self.ACCUMCO,
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o_SIGNEXTOUT=self.SIGNEXTOUT,
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)
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return m
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def elaborate_simulation(self):
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m = Module()
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p = self.parameters
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assert p["NEG_TRIGGER"] == 0, "Falling edge input clock polarity not supported in simulation."
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# Internal wire, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
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# http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
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# https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
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iA = Signal(16)
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iB = Signal(16)
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iC = Signal(16)
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iD = Signal(16)
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iF = Signal(16)
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iJ = Signal(16)
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iK = Signal(16)
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iG = Signal(16)
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iL = Signal(32)
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iH = Signal(32)
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iW = Signal(16)
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iX = Signal(16)
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iP = Signal(16)
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iQ = Signal(16)
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iY = Signal(16)
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iZ = Signal(16)
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iR = Signal(16)
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iS = Signal(16)
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HCI = Signal()
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LCI = Signal()
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LCO = Signal()
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# Registers
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rC = Signal(16)
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rA = Signal(16)
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rB = Signal(16)
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rD = Signal(16)
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rF = Signal(16)
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rJ = Signal(16)
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rK = Signal(16)
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rG = Signal(16)
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rH = Signal(32)
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rQ = Signal(16)
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rS = Signal(16)
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# Regs C and A
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with m.If(self.IRSTTOP):
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m.d.sync += [
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rC.eq(0),
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rA.eq(0),
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]
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with m.Elif(self.CE):
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with m.If(~self.CHOLD):
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m.d.sync += rC.eq(self.C)
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with m.If(~self.AHOLD):
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m.d.sync += rA.eq(self.A)
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m.d.comb += [
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iC.eq(rC if p["C_REG"] else self.C),
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iA.eq(rA if p["A_REG"] else self.A),
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]
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# Regs B and D
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with m.If(self.IRSTBOT):
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m.d.sync += [
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rB.eq(0),
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rD.eq(0)
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]
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with m.Elif(self.CE):
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with m.If(~self.BHOLD):
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m.d.sync += rB.eq(self.B)
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with m.If(~self.DHOLD):
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m.d.sync += rD.eq(self.D)
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m.d.comb += [
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iB.eq(rB if p["B_REG"] else self.B),
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iD.eq(rD if p["D_REG"] else self.D),
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]
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# Multiplier Stage
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p_Ah_Bh = Signal(16)
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p_Al_Bh = Signal(16)
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p_Ah_Bl = Signal(16)
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p_Al_Bl = Signal(16)
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Ah = Signal(16)
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Al = Signal(16)
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Bh = Signal(16)
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Bl = Signal(16)
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m.d.comb += [
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Ah.eq(Cat(iA[8:16], Mux(p["A_SIGNED"], iA[15].replicate(8), 0))),
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Al.eq(Cat(iA[0:8], Mux(p["A_SIGNED"] & p["MODE_8x8"], iA[7].replicate(8), 0))),
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Bh.eq(Cat(iB[8:16], Mux(p["B_SIGNED"], iB[15].replicate(8), 0))),
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Bl.eq(Cat(iB[0:8], Mux(p["B_SIGNED"] & p["MODE_8x8"], iB[7].replicate(8), 0))),
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p_Ah_Bh.eq(Ah * Bh), # F
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p_Al_Bh.eq(Al[0:8] * Bh), # J
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p_Ah_Bl.eq(Ah * Bl[0:8]), # K
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p_Al_Bl.eq(Al * Bl), # G
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]
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# Regs F and J
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with m.If(self.IRSTTOP):
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m.d.sync += [
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rF.eq(0),
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rJ.eq(0)
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]
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with m.Elif(self.CE):
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m.d.sync += rF.eq(p_Ah_Bh)
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if not p["MODE_8x8"]:
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m.d.sync += rJ.eq(p_Al_Bh)
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m.d.comb += [
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iF.eq(rF if p["TOP_8x8_MULT_REG"] else p_Ah_Bh),
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iJ.eq(rJ if p["PIPELINE_16x16_MULT_REG1"] else p_Al_Bh),
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]
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# Regs K and G
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with m.If(self.IRSTBOT):
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m.d.sync += [
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rK.eq(0),
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rG.eq(0)
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]
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with m.Elif(self.CE):
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with m.If(~p["MODE_8x8"]):
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m.d.sync += rK.eq(p_Ah_Bl)
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m.d.sync += rG.eq(p_Al_Bl)
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m.d.comb += [
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iK.eq(rK if p["PIPELINE_16x16_MULT_REG1"] else p_Ah_Bl),
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iG.eq(rG if p["BOT_8x8_MULT_REG"] else p_Al_Bl),
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]
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# Adder Stage
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iK_e = Signal(24)
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iJ_e = Signal(24)
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m.d.comb += [
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iK_e.eq(Cat(iK, Mux(p["A_SIGNED"], iK[15].replicate(8), 0))),
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iJ_e.eq(Cat(iJ, Mux(p["B_SIGNED"], iJ[15].replicate(8), 0))),
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iL.eq(iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16)),
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]
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# Reg H
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with m.If(self.IRSTBOT):
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m.d.sync += rH.eq(0)
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with m.Elif(self.CE):
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if not p["MODE_8x8"]:
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m.d.sync += rH.eq(iL)
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m.d.comb += iH.eq(rH if p["PIPELINE_16x16_MULT_REG2"] else iL)
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# Hi Output Stage
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XW = Signal(17)
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Oh = Signal(16)
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m.d.comb += [
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iW.eq([iQ, iC][p["TOPADDSUB_UPPERINPUT"]]),
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iX.eq([iA, iF, iH[16:32], iZ[15].replicate(16)][p["TOPADDSUB_LOWERINPUT"]]),
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XW.eq(iX + (iW ^ self.ADDSUBTOP.replicate(16)) + HCI),
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self.ACCUMCO.eq(XW[16]),
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self.CO.eq(self.ACCUMCO ^ self.ADDSUBTOP),
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iP.eq(Mux(self.OLOADTOP, iC, XW[0:16] ^ self.ADDSUBTOP.replicate(16))),
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]
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with m.If(self.ORSTTOP):
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m.d.sync += rQ.eq(0)
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with m.Elif(self.CE):
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with m.If(~self.OHOLDTOP):
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m.d.sync += rQ.eq(iP)
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m.d.comb += [
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iQ.eq(rQ),
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Oh.eq([iP, iQ, iF, iH[16:32]][p["TOPOUTPUT_SELECT"]]),
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HCI.eq([0, 1, LCO, LCO ^ self.ADDSUBBOT][p["TOPADDSUB_CARRYSELECT"]]),
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self.SIGNEXTOUT.eq(iX[15]),
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]
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# Lo Output Stage
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YZ = Signal(17)
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Ol = Signal(16)
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m.d.comb += [
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iY.eq([iS, iD][p["BOTADDSUB_UPPERINPUT"]]),
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iZ.eq([iB, iG, iH[0:16], self.SIGNEXTIN.replicate(16)][p["BOTADDSUB_LOWERINPUT"]]),
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YZ.eq(iZ + (iY ^ self.ADDSUBBOT.replicate(16)) + LCI),
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LCO.eq(YZ[16]),
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iR.eq(Mux(self.OLOADBOT, iD, YZ[0:16] ^ self.ADDSUBBOT.replicate(16))),
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]
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with m.If(self.ORSTBOT):
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m.d.sync += rS.eq(0)
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with m.Elif(self.CE):
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with m.If(~self.OHOLDBOT):
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m.d.sync += rS.eq(iR)
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m.d.comb += [
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iS.eq(rS),
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Ol.eq([iR, iS, iG, iH[0:16]][p["BOTOUTPUT_SELECT"]]),
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LCI.eq([0, 1, self.ACCUMCI, self.CI][p["BOTADDSUB_CARRYSELECT"]]),
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self.O.eq(Cat(Ol, Oh)),
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]
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return m
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