mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-02-20 00:33:48 +01:00
409acbc3c9
Co-authored-by: mndza <diego.hdmp@gmail.com> Co-authored-by: Martin Ling <martin-git@earth.li> Co-authored-by: Antoine van Gelder <antoine@greatscottgadgets.com>
91 lines
3.2 KiB
Python
91 lines
3.2 KiB
Python
#!/usr/bin/env python3
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#
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# This file is part of HackRF.
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#
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# Copyright (c) 2024 Great Scott Gadgets <info@greatscottgadgets.com>
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# SPDX-License-Identifier: BSD-3-Clause
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from amaranth import Elaboratable, Signal, Instance, Module, ClockDomain
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from amaranth.build import Resource, Pins, Clock, Attrs
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from amaranth.vendor import LatticeICE40Platform
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from amaranth_boards.resources import SPIResource
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__all__ = ["PralinePlatform", "ClockDomainGenerator"]
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class PralinePlatform(LatticeICE40Platform):
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device = "iCE40UP5K"
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package = "SG48"
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default_clk = "SB_HFOSC" # 48 MHz internal oscillator
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hfosc_div = 0 # Do not divide
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resources = [
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Resource("fpga_clk", 0, Pins("39", dir="i"),
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Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
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# ADC/DAC interfaces.
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Resource("afe_clk", 0, Pins("35", dir="i"),
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Clock(40e6), Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
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Resource("dd", 0, Pins("38 37 36 34 32 31 28 27 26 25", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("da", 0, Pins("46 45 44 43 42 41 40 39", dir="i"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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# SGPIO interface.
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Resource("host_clk", 0, Pins("20", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("host_data", 0, Pins("21 19 6 13 10 3 4 18", dir="io"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("q_invert", 0, Pins("9", dir="i"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("direction", 0, Pins("12", dir="i"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("disable", 0, Pins("23", dir="i"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("capture_en", 0, Pins("11", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("trigger_in", 0, Pins("48", dir="i"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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Resource("trigger_out", 0, Pins("2", dir="o"),
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Attrs(IO_STANDARD="SB_LVCMOS")),
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# SPI can be used after configuration.
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SPIResource("spi", 0, role="peripheral",
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cs_n="16", clk="15", copi="17", cipo="14",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
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),
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]
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connectors = []
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class ClockDomainGenerator(Elaboratable):
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@staticmethod
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def lut_delay(m, signal, *, depth):
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signal_out = signal
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for i in range(depth):
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signal_in = signal_out
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signal_out = Signal()
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=0xAAAA, # Buffer configuration
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i_I0=signal_in,
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o_O=signal_out,
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)
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return signal_out
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def elaborate(self, platform):
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m = Module()
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# Define clock domains.
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m.domains.gck1 = cd_gck1 = ClockDomain(name="gck1", reset_less=True) # analog front-end clock.
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# We need to delay `gck1` clock by at least 8ns, not possible with the PLL alone.
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# Each LUT introduces a minimum propagation delay of 9ns (best case).
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delayed_gck1 = self.lut_delay(m, platform.request("afe_clk").i, depth=2)
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m.d.comb += cd_gck1.clk.eq(delayed_gck1)
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platform.add_clock_constraint(delayed_gck1, 40e6)
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return m
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