mirror of
https://github.com/greatscottgadgets/hackrf.git
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126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/*
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* Copyright 2024 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "ice40_spi.h"
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#include <libopencm3/lpc43xx/scu.h>
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#include "hackrf_core.h"
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#include "lz4_buf.h"
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#include "delay.h"
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void ice40_spi_target_init(ice40_spi_driver_t* const drv)
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{
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/* Configure SSP1 Peripheral and relevant FPGA pins. */
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scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
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scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
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scu_pinmux(SCU_PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
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scu_pinmux(SCU_PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
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scu_pinmux(SCU_PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
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/* Configure GPIOs as inputs or outputs as needed. */
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gpio_clear(drv->gpio_creset);
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gpio_output(drv->gpio_creset);
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gpio_input(drv->gpio_cdone);
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// select is configured in SSP code
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}
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uint8_t ice40_spi_read(ice40_spi_driver_t* const drv, uint8_t r)
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{
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uint8_t value[3] = {r & 0x7F, 0, 0};
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spi_bus_transfer(drv->bus, value, 3);
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return value[2];
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}
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void ice40_spi_write(ice40_spi_driver_t* const drv, uint8_t r, uint16_t v)
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{
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uint8_t value[3] = {(r & 0x7F) | 0x80, v, 0};
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spi_bus_transfer(drv->bus, value, 3);
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}
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static void spi_ssp1_wait_for_tx_fifo_not_full(void)
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{
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while ((SSP_SR(SSP1_BASE) & SSP_SR_TNF) == 0) {}
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}
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static void spi_ssp1_wait_for_rx_fifo_not_empty(void)
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{
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while ((SSP_SR(SSP1_BASE) & SSP_SR_RNE) == 0) {}
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}
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static void spi_ssp1_wait_for_not_busy(void)
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{
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while (SSP_SR(SSP1_BASE) & SSP_SR_BSY) {}
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}
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static uint32_t spi_ssp1_transfer_word(const uint32_t data)
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{
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spi_ssp1_wait_for_tx_fifo_not_full();
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SSP_DR(SSP1_BASE) = data;
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spi_ssp1_wait_for_not_busy();
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spi_ssp1_wait_for_rx_fifo_not_empty();
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return SSP_DR(SSP1_BASE);
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}
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bool ice40_spi_syscfg_program(
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ice40_spi_driver_t* const drv,
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size_t (*read_block_cb)(void* ctx, uint8_t* buffer),
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void* read_ctx)
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{
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// Drive CRESET_B = 0, SPI_SS = 0, SPI_SCK = 1.
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gpio_clear(drv->gpio_creset);
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gpio_clear(drv->gpio_select);
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// Wait a minimum of 200 ns.
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delay_us_at_mhz(1, 204 / 4); // 250 ns.
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// Release CRESET_B or drive CRESET_B = 1.
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gpio_set(drv->gpio_creset);
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// Wait a minimum of 1200 μs to clear internal configuration memory.
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// Testing showed us that we need to wait longer. Let's wait 1800 μs.
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delay_us_at_mhz(1800, 204);
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// Set SPI_SS = 1, Send 8 dummy clocks.
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gpio_set(drv->gpio_select);
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spi_ssp1_transfer_word(0);
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// Send configuration image serially on SPI_SI to iCE40, most-significant bit
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// first, on falling edge of SPI_SCK.
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gpio_clear(drv->gpio_select);
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for (;;) {
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size_t read_sz = read_block_cb(read_ctx, lz4_out_buf);
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if (read_sz == 0)
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break;
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for (size_t j = 0; j < read_sz; j++) {
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spi_ssp1_transfer_word(lz4_out_buf[j]);
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}
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}
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// Wait for 100 clocks cycles for CDONE to go high.
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gpio_set(drv->gpio_select);
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for (size_t j = 0; j < 13; j++) {
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spi_ssp1_transfer_word(0);
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}
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return gpio_read(drv->gpio_cdone);
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}
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