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https://github.com/greatscottgadgets/hackrf.git
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75 lines
2.6 KiB
C
75 lines
2.6 KiB
C
/* -*- mode: c -*-
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*
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* Copyright 2012 Michael Ossmann
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* Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __FPGA_REGS_DEF
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#define __FPGA_REGS_DEF
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#define FPGA_REG_SET_CLEAN(_d, _r) (_d->regs_dirty &= ~(1UL<<_r))
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#define FPGA_REG_SET_DIRTY(_d, _r) (_d->regs_dirty |= (1UL<<_r))
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/* Generate static inline accessors that operate on the global
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* regs. Done this way to (1) allow defs to be scraped out and used
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* elsewhere, e.g. in scripts, (2) to avoid dealing with endian
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* (structs). This may be used in firmware, or on host predefined
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* register loads. */
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/* On set_, register is always set dirty, even if nothing
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* changed. This makes sure that writes that have side effects,
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* e.g. frequency setting, are not skipped. */
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/* n=name, r=regnum, o=offset (bits from LSB) of LSB of field,
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* l=length (bits) */
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#define __MREG__(n,r,o,l) \
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static inline uint8_t get_##n(fpga_driver_t* const _d) { \
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return (_d->regs[r] >> o) & ((1L<<l)-1); \
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} \
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static inline void set_##n(fpga_driver_t* const _d, uint8_t v) { \
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_d->regs[r] &= (uint8_t)(~(((1L<<l)-1)<<o)); \
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_d->regs[r] |= (uint8_t)(((v&((1L<<l)-1))<<o)); \
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FPGA_REG_SET_DIRTY(_d, r); \
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} \
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const uint8_t n = r;
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/* REG 01 (1): CTRL */
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__MREG__(FPGA_STANDARD_CTRL, 1, 0, 8)
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__MREG__(FPGA_STANDARD_CTRL_DC_BLOCK, 1, 0, 1)
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__MREG__(FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN, 1, 1, 1)
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__MREG__(FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP, 1, 2, 1)
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__MREG__(FPGA_STANDARD_CTRL_PRBS, 1, 6, 1)
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__MREG__(FPGA_STANDARD_CTRL_TRIGGER_EN, 1, 7, 1)
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/* REG 02 (2): RX_DECIM */
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__MREG__(FPGA_STANDARD_RX_DECIM, 2, 0, 3)
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/* REG 03 (3): TX_CTRL */
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__MREG__(FPGA_STANDARD_TX_CTRL, 3, 0, 1)
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__MREG__(FPGA_STANDARD_TX_CTRL_NCO_EN, 3, 0, 1)
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/* REG 04 (4): TX_INTRP */
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__MREG__(FPGA_STANDARD_TX_INTRP, 4, 0, 3)
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/* REG 05 (5): TX_PSTEP */
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__MREG__(FPGA_STANDARD_TX_PSTEP, 5, 0, 8)
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#endif // __FPGA_REGS_DEF
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