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https://github.com/greatscottgadgets/hackrf.git
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111 lines
4.4 KiB
Python
111 lines
4.4 KiB
Python
#
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# This file is part of HackRF.
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#
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# Copyright (c) 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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# SPDX-License-Identifier: BSD-3-Clause
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from amaranth import Elaboratable, Module, Cat, DomainRenamer
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from amaranth.lib.wiring import connect
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from amaranth_future import fixed
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from board import PralinePlatform, ClockDomainGenerator
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from interface import MAX586xInterface, SGPIOInterface, SPIRegisterInterface
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from dsp.fir import FIRFilter
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from dsp.fir_mac16 import HalfBandDecimatorMAC16
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from dsp.cic import CICDecimator
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from dsp.dc_block import DCBlock
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from dsp.quarter_shift import QuarterShift
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from util import ClockConverter, IQSample
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class Top(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.clkgen = ClockDomainGenerator()
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# Submodules.
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m.submodules.adcdac_intf = adcdac_intf = MAX586xInterface(bb_domain="gck1")
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m.submodules.mcu_intf = mcu_intf = SGPIOInterface(
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sample_width=24,
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rx_assignments=[
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lambda w: Cat(w[8:12], w[11].replicate(4)),
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lambda w: w[0:8],
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lambda w: Cat(w[20:24], w[23].replicate(4)),
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lambda w: w[12:20],
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],
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tx_assignments=[
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lambda w, v: w[8:12].eq(v),
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lambda w, v: w[0:8].eq(v),
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lambda w, v: w[20:24].eq(v),
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lambda w, v: w[12:20].eq(v),
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],
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domain="sync"
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)
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m.d.comb += adcdac_intf.q_invert.eq(platform.request("q_invert").i)
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# Half-band filter taps.
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taps_hb1 = [-2, 0, 5, 0, -10, 0,18, 0, -30, 0,53, 0,-101, 0, 323, 512, 323, 0,-101, 0, 53, 0, -30, 0,18, 0, -10, 0, 5, 0,-2]
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taps_hb1 = [ tap/1024 for tap in taps_hb1 ]
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taps_hb2 = [ -6, 0, 19, 0, -44, 0, 89, 0, -163, 0, 278, 0, -452, 0, 711, 0, -1113, 0, 1800, 0, -3298, 0, 10370, 16384, 10370, 0, -3298, 0, 1800, 0, -1113, 0, 711, 0, -452, 0, 278, 0, -163, 0, 89, 0, -44, 0, 19, 0, -6]
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taps_hb2 = [ tap/16384/2 for tap in taps_hb2 ]
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rx_chain = {
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# DC block and quarter shift.
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"dc_block": DCBlock(width=8, num_channels=2, domain="gck1"),
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"quarter_shift": DomainRenamer("gck1")(QuarterShift()),
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# CIC mandatory first stage with compensator.
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"cic": CICDecimator(2, 4, (4,8,16,32), width_in=8, width_out=12, num_channels=2, always_ready=True, domain="gck1"),
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"cic_comp": DomainRenamer("gck1")(FIRFilter([-0.125, 0, 0.75, 0, -0.125], shape=fixed.SQ(11), shape_out=fixed.SQ(11), always_ready=True, num_channels=2)),
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# Final half-band decimator stages.
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"hbfir1": HalfBandDecimatorMAC16(taps_hb1, data_shape=fixed.SQ(11), overclock_rate=4, always_ready=True, domain="gck1"),
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"hbfir2": HalfBandDecimatorMAC16(taps_hb2, data_shape=fixed.SQ(11), overclock_rate=8, always_ready=True, domain="gck1"),
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# Clock domain conversion.
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"clkconv": ClockConverter(IQSample(12), 8, "gck1", "sync", always_ready=True),
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}
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for k,v in rx_chain.items():
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m.submodules[f"rx_{k}"] = v
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# Connect receiver chain.
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last = adcdac_intf.adc_stream
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for block in rx_chain.values():
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connect(m, last, block.input)
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last = block.output
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connect(m, last, mcu_intf.adc_stream)
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# SPI register interface.
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spi_port = platform.request("spi")
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m.submodules.spi_regs = spi_regs = SPIRegisterInterface(spi_port)
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# Add control registers.
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ctrl = spi_regs.add_register(0x01, init=0)
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rx_decim = spi_regs.add_register(0x02, init=0, size=3)
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#tx_intrp = spi_regs.add_register(0x04, init=0, size=3)
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m.d.comb += [
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# Trigger enable.
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mcu_intf.trigger_en .eq(ctrl[7]),
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# RX settings.
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rx_chain["dc_block"].enable .eq(ctrl[0]),
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rx_chain["quarter_shift"].enable .eq(ctrl[1]),
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rx_chain["quarter_shift"].up .eq(ctrl[2]),
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# RX decimation rate.
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rx_chain["cic"].factor .eq(rx_decim+2),
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]
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return m
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if __name__ == "__main__":
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plat = PralinePlatform()
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plat.build(Top())
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