mirror of
https://github.com/greatscottgadgets/hackrf.git
synced 2026-03-03 05:55:18 +01:00
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/*
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* Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hackrf_core.h"
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#include "lz4_blk.h"
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#include "lz4_buf.h"
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#include "selftest.h"
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// FPGA bitstreams blob.
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extern uint32_t _binary_fpga_bin_start;
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extern uint32_t _binary_fpga_bin_end;
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extern uint32_t _binary_fpga_bin_size;
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struct fpga_image_read_ctx {
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uint32_t addr;
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size_t next_block_sz;
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uint8_t init_flag;
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};
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static size_t fpga_image_read_block_cb(void* _ctx, uint8_t* out_buffer)
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{
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// Assume out_buffer is 4KB
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struct fpga_image_read_ctx* ctx = _ctx;
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size_t block_sz = ctx->next_block_sz;
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uint8_t block_sz_buf[2];
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// first iteration: read first block size
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if (ctx->init_flag == 0) {
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w25q80bv_read(&spi_flash, ctx->addr, 2, block_sz_buf);
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block_sz = block_sz_buf[0] | block_sz_buf[1] << 8;
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ctx->addr += 2;
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ctx->init_flag = 1;
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}
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// finish at end marker
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if (block_sz == 0)
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return 0;
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// Read compressed block (and the next block size) from flash.
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w25q80bv_read(&spi_flash, ctx->addr, block_sz, lz4_in_buf);
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ctx->addr += block_sz;
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w25q80bv_read(&spi_flash, ctx->addr, 2, block_sz_buf);
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ctx->next_block_sz = block_sz_buf[0] | block_sz_buf[1] << 8;
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ctx->addr += 2;
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// Decompress block.
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return lz4_blk_decompress(lz4_in_buf, out_buffer, block_sz);
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}
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bool fpga_image_load(unsigned int index)
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{
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#if defined(DFU_MODE) || defined(RAM_MODE)
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selftest.fpga_image_load = SKIPPED;
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selftest.report.pass = false;
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return false;
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#endif
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// TODO: do SPI setup and read number of bitstreams once!
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// Prepare for SPI flash access.
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spi_bus_start(spi_flash.bus, &ssp_config_w25q80bv);
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w25q80bv_setup(&spi_flash);
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// Read number of bitstreams from flash.
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// Check the bitstream exists, and extract its offset.
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uint32_t addr = (uint32_t) &_binary_fpga_bin_start;
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uint32_t num_bitstreams, bitstream_offset;
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w25q80bv_read(&spi_flash, addr, 4, (uint8_t*) &num_bitstreams);
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if (index >= num_bitstreams)
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return false;
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w25q80bv_read(&spi_flash, addr + 4 * (index + 1), 4, (uint8_t*) &bitstream_offset);
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// A callback function is used by the FPGA programmer
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// to obtain consecutive gateware chunks.
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ice40_spi_target_init(&ice40);
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ssp1_set_mode_ice40();
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struct fpga_image_read_ctx fpga_image_ctx = {
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.addr = (uint32_t) &_binary_fpga_bin_start + bitstream_offset,
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};
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const bool success = ice40_spi_syscfg_program(
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&ice40,
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fpga_image_read_block_cb,
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&fpga_image_ctx);
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ssp1_set_mode_max283x();
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// Update selftest result.
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selftest.fpga_image_load = success ? PASSED : FAILED;
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if (selftest.fpga_image_load != PASSED) {
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selftest.report.pass = false;
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}
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return success;
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}
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