mirror of
https://github.com/greatscottgadgets/hackrf.git
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84 lines
2.9 KiB
C
84 lines
2.9 KiB
C
/*
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* Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __FPGA_H
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#define __FPGA_H
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#include <stdbool.h>
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#include "ice40_spi.h"
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/* Up to 6 registers, each containing up to 8 bits of data */
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#define FPGA_NUM_REGS 6
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#define FPGA_DATA_REGS_MAX_VALUE 255
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typedef enum {
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FPGA_QUARTER_SHIFT_MODE_NONE = 0b00,
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FPGA_QUARTER_SHIFT_MODE_UP = 0b11,
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FPGA_QUARTER_SHIFT_MODE_DOWN = 0b01,
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} fpga_quarter_shift_mode_t;
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struct fpga_driver_t;
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typedef struct fpga_driver_t fpga_driver_t;
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struct fpga_driver_t {
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ice40_spi_driver_t* bus;
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uint8_t regs[FPGA_NUM_REGS];
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uint8_t regs_dirty;
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};
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/* Initialize the loaded bitstream's registers to their default values. */
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extern void fpga_init(fpga_driver_t* const drv);
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/* Initialize fpga and gateware. */
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extern void fpga_setup(fpga_driver_t* const drv);
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/* Read a register via SPI. Save a copy to memory and return
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* value. Mark clean. */
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extern uint8_t fpga_reg_read(fpga_driver_t* const drv, uint8_t r);
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/* Write value to register via SPI and save a copy to memory. Mark
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* clean. */
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extern void fpga_reg_write(fpga_driver_t* const drv, uint8_t r, uint8_t v);
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/* Write all dirty registers via SPI from memory. Mark all clean. Some
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* operations require registers to be written in a certain order. Use
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* provided routines for those operations. */
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extern void fpga_regs_commit(fpga_driver_t* const drv);
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void fpga_set_trigger_enable(fpga_driver_t* const drv, const bool enable);
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void fpga_set_rx_dc_block_enable(fpga_driver_t* const drv, const bool enable);
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void fpga_set_rx_decimation_ratio(fpga_driver_t* const drv, const uint8_t value);
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void fpga_set_rx_quarter_shift_mode(
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fpga_driver_t* const drv,
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const fpga_quarter_shift_mode_t mode);
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void fpga_set_tx_interpolation_ratio(fpga_driver_t* const drv, const uint8_t value);
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void fpga_set_prbs_enable(fpga_driver_t* const drv, const bool enable);
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void fpga_set_tx_nco_enable(fpga_driver_t* const drv, const bool enable);
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void fpga_set_tx_nco_pstep(fpga_driver_t* const drv, const uint8_t phase_increment);
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bool fpga_image_load(unsigned int index);
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bool fpga_spi_selftest(void);
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bool fpga_sgpio_selftest(void);
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bool fpga_if_xcvr_selftest(void);
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#endif // __FPGA_H
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