Commit Graph

  • 3bf6573dc6 Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller. Updated SGPIO CPLD testbench, as it had fallen a bit out of date. Add SGPIO API initialization and control of CPLD decimation feature. Jared Boone 2013-11-19 19:52:06 -08:00
  • 24a8e2bdb5 Remove CPLD SVF file, as it's not used by anybody (as far as I know). Jared Boone 2013-11-19 19:45:36 -08:00
  • 5b14636c2c initial firmware support for HackRF One Michael Ossmann 2013-11-19 10:01:26 -07:00
  • 967e699815 Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values. Jared Boone 2013-11-17 22:23:08 -08:00
  • a909ca641c moved GCK1 test point Michael Ossmann 2013-11-16 21:39:15 -07:00
  • ca2162da29 forgot to save schematic Michael Ossmann 2013-11-16 21:26:07 -07:00
  • 95ffc704a1 P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28 Michael Ossmann 2013-11-16 21:22:25 -07:00
  • d006ec769c Updated CPLD bitstream with two's complement I/O and sample ordering fix. Jared Boone 2013-11-16 13:41:54 -08:00
  • 89eafaa79a Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this. Jared Boone 2013-11-16 13:32:41 -08:00
  • 7ef9c1e932 Slow down edges of data lines coming from CPLD. Jared Boone 2013-11-16 13:31:19 -08:00
  • 147f47a3f5 Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed. Do conversion from unsigned to two's-compliment inside FPGA. Jared Boone 2013-11-16 13:29:00 -08:00
  • 9856ea3d14 Changes due to CGU header API changes. Jared Boone 2013-11-15 11:41:20 -08:00
  • db3ef109fa forgot to save schematic when adding clock signals to header Michael Ossmann 2013-11-11 20:56:47 -07:00
  • 06f345239b silkscreen tweaks Michael Ossmann 2013-11-11 20:49:57 -07:00
  • fecc7346b3 GND test points Michael Ossmann 2013-11-11 19:25:28 -07:00
  • a8c2c0b6d1 more decoupling caps Michael Ossmann 2013-11-11 19:07:28 -07:00
  • 26104e6735 nudged some traces in the RF section Michael Ossmann 2013-11-11 18:48:39 -07:00
  • c5533b3c96 reworked zones so LED signals do not cross power planes Michael Ossmann 2013-11-11 18:04:45 -07:00
  • 515b6973aa exposed GCK1, GCK2 on expansion P28 instead of extra CPLD pins. also ditched 1V8 on P30 Michael Ossmann 2013-11-11 17:23:45 -07:00
  • f576fc27f0 rerouted 1V8 Michael Ossmann 2013-11-11 16:58:30 -07:00
  • 1b3da372b9 CPLD JTAG cleanup Michael Ossmann 2013-11-11 16:37:43 -07:00
  • 4577439912 keep GCK1 on front side Michael Ossmann 2013-11-11 16:32:37 -07:00
  • 174c3b427b still cleaning Michael Ossmann 2013-11-11 11:09:48 -07:00
  • fbcc3b60ec still more clean-up Michael Ossmann 2013-11-11 10:57:08 -07:00
  • 923971402c a little more clean-up Michael Ossmann 2013-11-11 10:51:12 -07:00
  • 976096f019 a little clean-up Michael Ossmann 2013-11-11 10:25:46 -07:00
  • f7e1b15cc9 more mounting holes Michael Ossmann 2013-11-11 10:04:29 -07:00
  • 20518a77d5 SPIFI test points Michael Ossmann 2013-11-10 23:17:48 -07:00
  • 5beef42bc5 track clean-up Michael Ossmann 2013-11-10 23:11:04 -07:00
  • d6b7202e64 corner holes Michael Ossmann 2013-11-10 20:23:04 -07:00
  • 198bc7afeb TVS diodes for CLKIN and CLKOUT Michael Ossmann 2013-11-10 20:19:38 -07:00
  • afba176de4 USB shield break-out Michael Ossmann 2013-11-10 20:11:00 -07:00
  • 1fa9c9aa04 many test points Michael Ossmann 2013-11-10 19:53:25 -07:00
  • 61176e5371 selected a new part for USB ESD protection Michael Ossmann 2013-11-10 16:49:26 -07:00
  • c5ca300a53 P22 consolidation, expansion Michael Ossmann 2013-11-09 23:32:45 -07:00
  • d5da6dfee7 VBUS passives just in case Michael Ossmann 2013-11-09 21:17:30 -07:00
  • 02781f6bc5 extra footprints for clock signal passives just in case Michael Ossmann 2013-11-09 19:45:17 -07:00
  • b915582f49 series resistors on RESET and DFU lines just in case Michael Ossmann 2013-11-09 18:52:55 -07:00
  • f139288f62 fixed SMA connector selection Michael Ossmann 2013-11-09 18:20:06 -07:00
  • 297639df6e chose a different button Michael Ossmann 2013-11-09 17:26:14 -07:00
  • ee5e6f1dfa paste layer cleanup Michael Ossmann 2013-11-09 13:35:10 -07:00
  • 6b1cd52246 connected RF shield Michael Ossmann 2013-11-09 12:56:09 -07:00
  • 08655a1fa1 new style PCB trace jumper to minimize DRC errors Michael Ossmann 2013-11-09 10:38:11 -07:00
  • 8b1d4aadf5 recovered unsaved schematic modifications Michael Ossmann 2013-11-09 10:24:02 -07:00
  • 2a04fa4d10 more DRC cleanup Michael Ossmann 2013-11-09 10:20:56 -07:00
  • 7c03751e21 DRC cleanup Michael Ossmann 2013-11-09 09:57:42 -07:00
  • 5fdb5634d2 placed SSP1 test points Michael Ossmann 2013-11-08 21:31:16 -07:00
  • 08a3f1cc13 VAA (RF supply) LED Michael Ossmann 2013-11-08 21:19:14 -07:00
  • 552bc451a8 right angle LEDs Michael Ossmann 2013-11-08 18:40:39 -07:00
  • 2edd0caa66 pushbutton component selection Michael Ossmann 2013-11-08 17:26:14 -07:00
  • 7dadbcb612 finished the trickiest digital signal routing Michael Ossmann 2013-11-07 17:12:34 -07:00
  • 42076ce57a P20 consolidation Michael Ossmann 2013-11-07 10:04:52 -07:00
  • 8720b84e3e started rearranging expansion headers Michael Ossmann 2013-11-06 23:24:51 -07:00
  • 62dd06fdc6 started back side routing Michael Ossmann 2013-11-06 20:59:54 -07:00
  • f7361217c1 CPLD expansion routing Michael Ossmann 2013-11-06 17:37:05 -07:00
  • e93158b4e5 clock signal routing Michael Ossmann 2013-11-06 16:54:24 -07:00
  • aad83b7118 supply zones Michael Ossmann 2013-11-06 16:17:06 -07:00
  • b2291ba5d9 SPI flash layout Michael Ossmann 2013-11-06 15:32:09 -07:00
  • 3ed0112672 misc. layout Michael Ossmann 2013-11-05 17:51:18 -07:00
  • a374c4191a CPLD JTAG header Michael Ossmann 2013-11-05 16:45:53 -07:00
  • b2a6dba955 cleaned up Si5351C layout Michael Ossmann 2013-11-05 16:28:29 -07:00
  • 4917c5019a Additional CGU register decoding in dump_cgu.py. Jared Boone 2013-11-02 22:51:35 -07:00
  • bef5835d54 USB, regulator layout Michael Ossmann 2013-11-01 18:10:49 -06:00
  • 4af6b1688b LPC4320 placed Michael Ossmann 2013-11-01 16:53:22 -06:00
  • 52c7f3297b CPLD layout Michael Ossmann 2013-11-01 00:03:15 -06:00
  • c7d8636858 hopeful Si5351C placement Michael Ossmann 2013-10-31 23:04:19 -06:00
  • aff2a579e3 MAX5864 layout, rearranged analog baseband headers Michael Ossmann 2013-10-31 22:44:55 -06:00
  • 17e469c979 analog baseband headers Michael Ossmann 2013-10-31 21:45:34 -06:00
  • 567417df04 RF section front side finished Michael Ossmann 2013-10-31 21:18:42 -06:00
  • 551e850550 more RF layout Michael Ossmann 2013-10-29 18:30:12 -06:00
  • 565a821e92 RF section rough component positions Michael Ossmann 2013-10-29 17:50:57 -06:00
  • dbcb2b3550 started RF layout Michael Ossmann 2013-10-29 15:16:02 -06:00
  • dccb8ee552 BMI-S-230 RF shield module Michael Ossmann 2013-10-28 18:46:37 -06:00
  • 60e66317d7 new board outline Michael Ossmann 2013-10-28 18:21:48 -06:00
  • e87234b8f9 big import of updates into pcbnew Michael Ossmann 2013-10-28 18:00:17 -06:00
  • c6bacf0e21 module selection update to agree with recent schematic changes Michael Ossmann 2013-10-28 17:06:49 -06:00
  • bd75823536 USB-MICROB-FCI-10103594 module: decreased drill sizes Michael Ossmann 2013-10-28 16:28:57 -06:00
  • 6c7352b797 QFN32 (RFFC5072) module: increased pad length by 50% Michael Ossmann 2013-10-28 16:07:20 -06:00
  • e87529df8b QFN20-4 (Si5351C) module: increased pad width a bit Michael Ossmann 2013-10-28 15:40:59 -06:00
  • 62e4176953 QFN20-4 (Si5351C) module: increased pad length by 50% Michael Ossmann 2013-10-28 15:33:14 -06:00
  • 25aaa2a881 SKY13350 module: doubled pad size Michael Ossmann 2013-10-28 15:22:29 -06:00
  • a90a57c5b9 SKY13317 module: increased pad length by 50% Michael Ossmann 2013-10-28 15:07:14 -06:00
  • 7bfd46597b USB0_ID pull-up Michael Ossmann 2013-10-25 18:15:19 -06:00
  • 0d59261ae3 removed RF switch logic ICs, replaced with direct GPIO Michael Ossmann 2013-10-25 18:05:03 -06:00
  • beccc70ad6 change to LPC4320 Michael Ossmann 2013-10-25 17:17:37 -06:00
  • e872bc45a9 broke out more I2S0 pins Michael Ossmann 2013-10-25 17:14:14 -06:00
  • 70a87a86aa added I2C1 to SSP0 header (all expansion headers are subject to rearranging during layout) Michael Ossmann 2013-10-25 17:02:19 -06:00
  • 1176bfe7e8 SSP0 header Michael Ossmann 2013-10-25 15:55:17 -06:00
  • b4e3d59ae4 VBUS header Michael Ossmann 2013-10-25 15:12:55 -06:00
  • e279702915 connected USB0 ID pin Michael Ossmann 2013-10-25 14:35:09 -06:00
  • 3ab5e3b991 high side switch for VAA (RF section power supply) Michael Ossmann 2013-10-25 14:24:27 -06:00
  • 3b07a93eea RTC expansion Michael Ossmann 2013-10-25 13:47:43 -06:00
  • d5fbf35545 fixed all clock generator output supplies to VCC Michael Ossmann 2013-10-24 14:56:34 -06:00
  • cbd3295cb3 fixed clock input and output to 3.3V CMOS Michael Ossmann 2013-10-24 14:42:03 -06:00
  • 0de2298d77 optional RTC XTAL Michael Ossmann 2013-09-29 21:21:50 -06:00
  • 40406e52ad removed more DNP parts Michael Ossmann 2013-09-29 20:54:36 -06:00
  • cda1462fff regulator feedback fix Michael Ossmann 2013-09-29 20:47:32 -06:00
  • c2ae30dd4b removed PCB antenna Michael Ossmann 2013-09-29 20:42:20 -06:00
  • 2626e1814d fixed MAX5864 OVDD to VCC Michael Ossmann 2013-09-29 19:19:03 -06:00
  • a9026c521f fixed VCCIO1 to VCC Michael Ossmann 2013-09-29 19:08:04 -06:00