diff --git a/firmware/common/tune_config.h b/firmware/common/tune_config.h
index 05c1b34a..dd21d028 100644
--- a/firmware/common/tune_config.h
+++ b/firmware/common/tune_config.h
@@ -36,24 +36,49 @@ typedef struct {
 /* tuning table optimized for TX */
 static const tune_config_t praline_tune_config_tx[] = {
 	{ 2100, 2375,  true, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 2175, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2105, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2115, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2130, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2150, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2160, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2175, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2190, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2195, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2210, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2248, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2265, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 2300, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 2320, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 2580,    0, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 3000, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3100, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3140, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 3200, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3350, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3280, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3340, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3420, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3480, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 3500, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3550, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3650, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3700, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3850, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 3925, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 4600, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3595, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3625, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3670, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3710, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3760, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3790, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3860, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 3915, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 4000, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 4055, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 4125, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 4700, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 4800, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 5100, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
-	{ 5850, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5000, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5260, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5465, 2525, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5560, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5720, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5860, 2475, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 5970, 2575, false, FPGA_QUARTER_SHIFT_MODE_NONE },
+	{ 6000, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 6500, 2325, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 6750, 2375, false, FPGA_QUARTER_SHIFT_MODE_NONE },
 	{ 6850, 2425, false, FPGA_QUARTER_SHIFT_MODE_NONE },
@@ -230,40 +255,33 @@ static const tune_config_t praline_tune_config_rx[] = {
 	{ 1675, 2560,  true, FPGA_QUARTER_SHIFT_MODE_UP   },
 	{ 1992, 2380,  true, FPGA_QUARTER_SHIFT_MODE_DOWN },
 	{ 2070, 2340,  true, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2161, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2180, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2188, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2194, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2195, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2150, 2360,  true, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2168, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2185, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2202, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
 	{ 2205, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2213, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2215, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2222, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2232, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2234, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2216, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2223, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2234, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
 	{ 2240, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2245, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2247, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2251, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2257, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2258, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2262, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2251, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2258, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
 	{ 2265, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2270, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2275, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2279, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2280, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2282, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2271, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2273, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2275, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2280, 2500, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
 	{ 2284, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2289, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2292, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2289, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
 	{ 2293, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2299, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2300, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
-	{ 2302, 2560, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2307, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2315, 2500, false, FPGA_QUARTER_SHIFT_MODE_UP   },
-	{ 2320, 2520, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2298, 2520, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2300, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2302, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2309, 2560, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2311, 2580, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2314, 2540, false, FPGA_QUARTER_SHIFT_MODE_UP   },
+	{ 2315, 2540, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
+	{ 2320, 2580, false, FPGA_QUARTER_SHIFT_MODE_UP   },
 	{ 2380,    0, false, FPGA_QUARTER_SHIFT_MODE_UP   },
 	{ 2440,    0, false, FPGA_QUARTER_SHIFT_MODE_DOWN },
 	{ 2500,    0, false, FPGA_QUARTER_SHIFT_MODE_UP   },