diff --git a/firmware/common/fpga.c b/firmware/common/fpga.c
index 5ac0bf95..a997d6b8 100644
--- a/firmware/common/fpga.c
+++ b/firmware/common/fpga.c
@@ -96,8 +96,8 @@ bool fpga_image_load(unsigned int index)
 
 	// A callback function is used by the FPGA programmer
 	// to obtain consecutive gateware chunks.
-	ssp1_set_mode_ice40();
 	ice40_spi_target_init(&ice40);
+	ssp1_set_mode_ice40();
 	struct fpga_image_read_ctx fpga_image_ctx = {
 		.addr = (uint32_t) &_binary_fpga_bin_start + bitstream_offset,
 	};
diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 215c5528..5e323ca7 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -1146,6 +1146,9 @@ void pin_setup(void)
 	scu_pinmux(SCU_TRIGGER_IN, SCU_TRIGGER_IN_PINCFG);
 	scu_pinmux(SCU_TRIGGER_OUT, SCU_TRIGGER_OUT_PINCFG);
 	scu_pinmux(SCU_PPS_OUT, SCU_PPS_OUT_PINCFG);
+	scu_pinmux(SCU_PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
 
 	p2_ctrl_set(P2_SIGNAL_CLK3);
 	p1_ctrl_set(P1_SIGNAL_CLKIN);
@@ -1162,6 +1165,11 @@ void pin_setup(void)
 	gpio_output(&gpio_aa_en);
 	gpio_input(&gpio_trigger_in);
 	gpio_input(&gpio_trigger_out);
+	gpio_clear(&gpio_fpga_cfg_spi_cs);
+	gpio_output(&gpio_fpga_cfg_spi_cs);
+	gpio_clear(&gpio_fpga_cfg_creset);
+	gpio_output(&gpio_fpga_cfg_creset);
+	gpio_input(&gpio_fpga_cfg_cdone);
 #endif
 
 	/* enable input on SCL and SDA pins */