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PLL1 was misconfigured to run at 408MHz (way out of spec) instead of 204MHz. Corrected this by using DIRECT=1 instead of FBSEL=1.

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Jared Boone
2013-05-11 12:11:37 -07:00
parent a4a2a3d6ba
commit d9884af8b8
1 changed files with 1 additions and 1 deletions
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firmware/common/hackrf_core.c
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@@ -252,7 +252,7 @@ void cpu_clock_init(void)
| CGU_PLL1_CTRL_PSEL(0)
| CGU_PLL1_CTRL_NSEL(0)
| CGU_PLL1_CTRL_MSEL(16)
| CGU_PLL1_CTRL_FBSEL;
| CGU_PLL1_CTRL_DIRECT;
/* wait until stable */
while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK));