diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
index 6fa850a6..7f5b750a 100644
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
@@ -351,7 +351,7 @@ static uint32_t gcd(uint32_t u, uint32_t v)
 
 bool sample_rate_frac_set(uint32_t rate_num, uint32_t rate_denom)
 {
-	const uint64_t VCO_FREQ = 800 * 1000 * 1000; /* 800 MHz */
+	const uint64_t VCO_FREQ = 850 * 1000 * 1000; /* 850 MHz VCO */
 	uint32_t MSx_P1, MSx_P2, MSx_P3;
 	uint32_t a, b, c;
 	uint32_t rem;
@@ -602,24 +602,24 @@ void cpu_clock_init(void)
 	si5351c_configure_multisynth(
 		&clock_gen,
 		4,
-		20 * 128 - 512,
+		22 * 128 - 512, // 850/22 MHz
 		0,
 		1,
-		0); /* 800/20 = 40MHz */
+		0);
 	/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
 	si5351c_configure_multisynth(
 		&clock_gen,
 		5,
-		20 * 128 - 512,
+		22 * 128 - 512, // 850/22 MHz
 		0,
 		1,
-		0); /* 800/20 = 40MHz */
+		0);
 
 	/* MS6/CLK6 is unused. */
 	/* MS7/CLK7 is unused. */
 
 	/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
-	sample_rate_set(10000000);
+	sample_rate_frac_set(10000000, 0);
 
 	si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
 	// soft reset
diff --git a/firmware/common/max2837.c b/firmware/common/max2837.c
index 5fdc2ea4..bdb319eb 100644
--- a/firmware/common/max2837.c
+++ b/firmware/common/max2837.c
@@ -226,11 +226,11 @@ void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq)
 		lna_band = MAX2837_LNAband_2_6;
 	}
 
-	/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
-	div_int = freq / 30000000;
-	div_rem = freq % 30000000;
+	/* ASSUME 850/22 MHz reference. Ratio = F*(4/3)/ref = F/28977273 */
+	div_cmp = 28977273;
+	div_int = freq / div_cmp;
+	div_rem = freq % div_cmp;
 	div_frac = 0;
-	div_cmp = 30000000;
 	for (i = 0; i < 20; i++) {
 		div_frac <<= 1;
 		div_cmp >>= 1;
diff --git a/firmware/common/rffc5071.c b/firmware/common/rffc5071.c
index ccd17b4b..20e445cb 100644
--- a/firmware/common/rffc5071.c
+++ b/firmware/common/rffc5071.c
@@ -216,9 +216,10 @@ void rffc5071_enable(rffc5071_driver_t* const drv)
 	rffc5071_regs_commit(drv);
 }
 
-#define LO_MAX       5400
-#define REF_FREQ     40
-#define FREQ_ONE_MHZ (1000 * 1000)
+#define LO_MAX           5400
+#define REF_FREQ_NUM_MHZ 850
+#define REF_FREQ_DENOM   22
+#define FREQ_ONE_MHZ     (1000 * 1000)
 
 /* configure frequency synthesizer in integer mode (lo in MHz) */
 uint64_t rffc5071_config_synth_int(rffc5071_driver_t* const drv, uint16_t lo)
@@ -255,14 +256,15 @@ uint64_t rffc5071_config_synth_int(rffc5071_driver_t* const drv, uint16_t lo)
 		set_RFFC5071_PLLCPL(drv, 2);
 	}
 
-	uint64_t tmp_n = ((uint64_t) fvco << 29ULL) / (fbkdiv * REF_FREQ);
+	uint64_t tmp_n =
+		((uint64_t) fvco << 29ULL) * REF_FREQ_DENOM / (fbkdiv * REF_FREQ_NUM_MHZ);
 	n = tmp_n >> 29ULL;
 
 	p1nmsb = (tmp_n >> 13ULL) & 0xffff;
 	p1nlsb = (tmp_n >> 5ULL) & 0xff;
 
-	tune_freq_hz = (REF_FREQ * (tmp_n >> 5ULL) * fbkdiv * FREQ_ONE_MHZ) /
-		(lodiv * (1 << 24ULL));
+	tune_freq_hz = (REF_FREQ_NUM_MHZ * (tmp_n >> 5ULL) * fbkdiv * FREQ_ONE_MHZ) /
+		(lodiv * (1 << 24ULL) * REF_FREQ_DENOM);
 
 	/* Path 2 */
 	set_RFFC5071_P2LODIV(drv, n_lo);
diff --git a/firmware/common/si5351c.c b/firmware/common/si5351c.c
index 394a6dd5..3bf7adaa 100644
--- a/firmware/common/si5351c.c
+++ b/firmware/common/si5351c.c
@@ -123,13 +123,14 @@ void si5351c_configure_pll_sources(si5351c_driver_t* const drv)
 /* MultiSynth NA (PLLA) and NB (PLLB) */
 void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv)
 {
-	/*PLLA: 25MHz XTAL * (0x0e00+512)/128 = 800mhz -> int mode */
-	uint8_t data[] = {26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00};
+	/* PLLA: 25 MHz XTAL * (0x0f00+512)/128 = 850 MHz */
+	uint8_t data[] = {26, 0x00, 0x01, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00};
 	si5351c_write(drv, data, sizeof(data));
 
-	/*PLLB: 10MHz CLKIN * (0x2600+512)/128 = 800mhz */
+	/* PLLB: 10 MHz CLKIN * (0x2880+512)/128 = 850 MHz */
 	data[0] = 34;
-	data[4] = 0x26;
+	data[4] = 0x28;
+	data[5] = 0x80;
 	si5351c_write(drv, data, sizeof(data));
 }
 
@@ -291,7 +292,7 @@ void si5351c_clkout_enable(si5351c_driver_t* const drv, uint8_t enable)
 	clkout_enabled = (enable > 0);
 
 	/* Configure clock to 10MHz */
-	si5351c_configure_multisynth(drv, 3, 80 * 128 - 512, 0, 1, 0);
+	si5351c_configure_multisynth(drv, 3, 85 * 128 - 512, 0, 1, 0);
 
 	si5351c_configure_clock_control(drv, active_clock_source);
 	si5351c_enable_clock_outputs(drv);