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77 lines
2.6 KiB
C
77 lines
2.6 KiB
C
/*
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vector - interrupt vector table
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Copyright (C) 2011 Pavel Semerad
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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typedef void @far (*intr_handler_t)(void);
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struct intr_vector {
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unsigned char intr_inst;
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intr_handler_t intr_handler;
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};
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#define INTR_OP 0x82
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#define INTR_VEC(func) { INTR_OP, (intr_handler_t)func }
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@far @interrupt void DefaultInterrupt (void) {
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return;
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}
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#define INTR_DEFAULT INTR_VEC(DefaultInterrupt)
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extern void _stext(); /* startup routine */
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extern void ppm_interrupt(void);
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extern void timer_interrupt(void);
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struct intr_vector const _vectab[] = {
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INTR_VEC(_stext), /* reset */
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INTR_DEFAULT, /* trap */
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INTR_DEFAULT, /* 0 TLI - External top level interrupt */
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INTR_DEFAULT, /* 1 AWU - Auto wakeup from halt */
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INTR_DEFAULT, /* 2 CLK - Clock controller */
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INTR_DEFAULT, /* 3 EXTI0 - Port A external interrupts */
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INTR_DEFAULT, /* 4 EXTI1 - Port B external interrupts */
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INTR_DEFAULT, /* 5 EXTI2 - Port C external interrupts */
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INTR_DEFAULT, /* 6 EXTI3 - Port D external interrupts */
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INTR_DEFAULT, /* 7 EXTI4 - Port E external interrupts */
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INTR_DEFAULT, /* 8 */
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INTR_DEFAULT, /* 9 */
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INTR_DEFAULT, /* 10 SPI - End of transfer */
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INTR_DEFAULT, /* 11 TIM1 - update/overflow/underflow/trigger/break */
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INTR_DEFAULT, /* 12 TIM1 - capture/compare */
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INTR_VEC(timer_interrupt),/* 13 TIM2 - update/overflow */
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INTR_DEFAULT, /* 14 TIM2 - capture/compare */
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INTR_VEC(ppm_interrupt),/* 15 TIM3 - update/overflow */
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INTR_DEFAULT, /* 16 TIM3 - capture/compare */
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INTR_DEFAULT, /* 17 */
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INTR_DEFAULT, /* 18 */
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INTR_DEFAULT, /* 19 I2C - interrupt */
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INTR_DEFAULT, /* 20 UART2 - Tx complete */
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INTR_DEFAULT, /* 21 UART2 - Receiver register DATA FULL */
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INTR_DEFAULT, /* 22 ADC1 - end of conversion */
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INTR_DEFAULT, /* 23 TIM4 - update/overflow */
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INTR_DEFAULT, /* 24 Flash - EOP/WR_PG_DIS */
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INTR_DEFAULT, /* 25 */
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INTR_DEFAULT, /* 26 */
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INTR_DEFAULT, /* 27 */
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INTR_DEFAULT, /* 28 */
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INTR_DEFAULT, /* 29 */
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};
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