mirror of
https://github.com/gbdk-2020/gbdk-2020.git
synced 2026-03-19 05:37:56 +01:00
465 lines
22 KiB
C
465 lines
22 KiB
C
/** @file gb/hardware.h
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Defines that let the GB's hardware registers be accessed
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from C.
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See the @ref Pandocs for more details on each register.
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*/
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#ifndef _HARDWARE_H
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#define _HARDWARE_H
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#include <types.h>
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#define __BYTES extern UBYTE
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#define __BYTE_REG extern volatile UBYTE
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#define __REG extern volatile SFR
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/** Memory map */
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__BYTES _VRAM[];
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__BYTES _VRAM8000[];
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__BYTES _VRAM8800[];
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__BYTES _VRAM9000[];
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__BYTES _SCRN0[];
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__BYTES _SCRN1[];
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__BYTES _SRAM[];
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__BYTES _RAM[];
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__BYTES _RAMBANK[];
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__BYTES _OAMRAM[];
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__BYTE_REG _IO[];
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__BYTE_REG _AUD3WAVERAM[];
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__BYTE_REG _HRAM[];
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/** MBC5 registers */
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__BYTE_REG rRAMG;
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__BYTE_REG rROMB0;
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__BYTE_REG rROMB1;
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__BYTE_REG rRAMB;
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/** MBC7 registers */
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__BYTE_REG rMBC7_SRAM_ENABLE_1;
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__BYTE_REG rMBC7_SRAM_ENABLE_2;
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__BYTE_REG rMBC7_LATCH_1;
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__BYTE_REG rMBC7_LATCH_2;
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__BYTE_REG rMBC7_ACCEL_X_LO;
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__BYTE_REG rMBC7_ACCEL_X_HI;
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__BYTE_REG rMBC7_ACCEL_Y_LO;
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__BYTE_REG rMBC7_ACCEL_Y_HI;
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#define MBC7_LATCH_ERASE 0x55u
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#define MBC7_LATCH_CAPTURE 0xAAu
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#define MBC7_SRAM_ENABLE_KEY_1 0x0Au
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#define MBC7_SRAM_ENABLE_KEY_2 0x40u
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/** IO Registers */
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__REG P1_REG; /**< Joystick register @see joypad(), add_JOY(), IEF_HILO, P1F_5, P1F_4, P1F_3, P1F_2, P1F_1, P1F_0, P1F_GET_DPAD, P1F_GET_BTN, P1F_GET_NONE */
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#define rP1 P1_REG
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#define P1F_5 0b00100000
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#define P1F_4 0b00010000
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#define P1F_3 0b00001000
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#define P1F_2 0b00000100
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#define P1F_1 0b00000010
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#define P1F_0 0b00000001
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#define P1F_GET_DPAD P1F_5
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#define P1F_GET_BTN P1F_4
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#define P1F_GET_NONE (P1F_4 | P1F_5)
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__REG SB_REG; /**< Serial IO data buffer */
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#define rSB SB_REG
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__REG SC_REG; /**< Serial IO control register */
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#define rSC SC_REG
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#define SIOF_XFER_START 0b10000000 /**< Serial IO: Start Transfer. Automatically cleared at the end of transfer */
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#define SIOF_CLOCK_INT 0b00000001 /**< Serial IO: Use Internal clock */
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#define SIOF_CLOCK_EXT 0b00000000 /**< Serial IO: Use External clock */
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#define SIOF_SPEED_1X 0b00000000 /**< Serial IO: If internal clock then 8KHz mode, 1KB/s (16Khz in CGB high-speed mode, 2KB/s) */
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#define SIOF_SPEED_32X 0b00000010 /**< Serial IO: **CGB-Mode ONLY** If internal clock then 256KHz mode, 32KB/s (512KHz in CGB high-speed mode, 64KB/s) */
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#define SIOF_B_CLOCK 0
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#define SIOF_B_SPEED 1
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#define SIOF_B_XFER_START 7
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#define SCF_START SIOF_XFER_START
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#define SCF_SOURCE SIOF_CLOCK_INT
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#define SCF_SPEED SIOF_SPEED_32X
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__REG DIV_REG; /**< Divider register */
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#define rDIV DIV_REG
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__REG TIMA_REG; /**< Timer counter */
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#define rTIMA TIMA_REG
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__REG TMA_REG; /**< Timer modulo */
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#define rTMA TMA_REG
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__REG TAC_REG; /**< Timer control */
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#define rTAC TAC_REG
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#define TACF_START 0b00000100
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#define TACF_STOP 0b00000000
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#define TACF_4KHZ 0b00000000
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#define TACF_16KHZ 0b00000011
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#define TACF_65KHZ 0b00000010
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#define TACF_262KHZ 0b00000001
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__REG IF_REG; /**< Interrupt flags: @ref IEF_HILO, @ref IEF_SERIAL, @ref IEF_TIMER, @ref IEF_STAT, @ref IEF_VBLANK */
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#define rIF IF_REG
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__REG NR10_REG; /**< Sound Channel 1, NR10: Sweep */
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#define rAUD1SWEEP NR10_REG /**< Sound Channel 1, NR10: Sweep */
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#define AUD1SWEEP_UP 0b00000000 /**< For Sound Channel 1, NR10: Sweep Addition, period increases */
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#define AUD1SWEEP_DOWN 0b00001000 /**< For Sound Channel 1, NR10: Sweep Subtraction, period decreases */
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#define AUD1SWEEP_TIME(x) ((x) << 4) /**< For Sound Channel 1, NR10: Sweep Time/Pace, Range: 0-7 */
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#define AUD1SWEEP_LENGTH(x) (x) /**< For Sound Channel 1, NR10: Sweep Length/Individual step, Range: 0-7 */
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__REG NR11_REG; /**< Sound Channel 1, NR11: Sound length/Wave pattern duty */
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#define rAUD1LEN NR11_REG /**< Sound Channel 1, NR11: Sound length/Wave pattern duty */
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__REG NR12_REG; /**< Sound Channel 1, NR12: Volume Envelope */
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#define rAUD1ENV NR12_REG /**< Sound Channel 1, NR12: Volume Envelope */
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__REG NR13_REG; /**< Sound Channel 1, NR13: Frequency Low */
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#define rAUD1LOW NR13_REG /**< Sound Channel 1, NR13: Frequency Low */
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__REG NR14_REG; /**< Sound Channel 1, NR14: Frequency High */
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#define rAUD1HIGH NR14_REG /**< Sound Channel 1, NR14: Frequency High */
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__REG NR21_REG; /**< Sound Channel 2, NR21_REG: Tone */
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#define rAUD2LEN NR21_REG /**< Sound Channel 2, NR21_REG: Tone */
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__REG NR22_REG; /**< Sound Channel 2, NR22_REG: Volume Envelope */
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#define rAUD2ENV NR22_REG /**< Sound Channel 2, NR22_REG: Volume Envelope */
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__REG NR23_REG; /**< Sound Channel 2, NR23_REG: Frequency data Low */
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#define rAUD2LOW NR23_REG /**< Sound Channel 2, NR23_REG: Frequency data Low */
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__REG NR24_REG; /**< Sound Channel 2, NR24_REG: Frequency data High */
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#define rAUD2HIGH NR24_REG /**< Sound Channel 2, NR24_REG: Frequency data High */
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__REG NR30_REG; /**< Sound Channel 3, NR30_REG: Sound on/off */
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#define rAUD3ENA NR30_REG /**< Sound Channel 3, NR30_REG: Sound on/off */
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__REG NR31_REG; /**< Sound Channel 3, NR31_REG: Sound Length */
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#define rAUD3LEN NR31_REG /**< Sound Channel 3, NR31_REG: Sound Length */
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__REG NR32_REG; /**< Sound Channel 3, NR32_REG: Select output level */
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#define rAUD3LEVEL NR32_REG/**< Sound Channel 3, NR32_REG: Select output level */
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__REG NR33_REG; /**< Sound Channel 3, NR33_REG: Frequency data Low */
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#define rAUD3LOW NR33_REG /**< Sound Channel 3, NR33_REG: Frequency data Low */
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__REG NR34_REG; /**< Sound Channel 3, NR34_REG: Frequency data High */
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#define rAUD3HIGH NR34_REG /**< Sound Channel 3, NR34_REG: Frequency data High */
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__REG NR41_REG; /**< Sound Channel 4, NR41_REG: Sound Length */
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#define rAUD4LEN NR41_REG /**< Sound Channel 4, NR41_REG: Sound Length */
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__REG NR42_REG; /**< Sound Channel 4, NR42_REG: Volume Envelope */
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#define rAUD4ENV NR42_REG /**< Sound Channel 4, NR42_REG: Volume Envelope */
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__REG NR43_REG; /**< Sound Channel 4, NR43_REG: Polynomial Counter */
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#define rAUD4POLY NR43_REG /**< Sound Channel 4, NR43_REG: Polynomial Counter */
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#define AUD4POLY_WIDTH_15BIT 0x00 /**< For Sound Channel 4, NR43_REG: Polynomial counter use 15 steps */
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#define AUD4POLY_WIDTH_7BIT 0x08 /**< For Sound Channel 4, NR43_REG: Polynomial counter use 7 steps */
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__REG NR44_REG; /**< Sound Channel 4, NR44_REG: Counter / Consecutive and Initial */
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#define rAUD4GO NR44_REG /**< Sound Channel 4, NR44_REG: Counter / Consecutive and Initial */
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__REG NR50_REG; /**< Sound Master Volume, NR50: Volume and Cart external sound input (VIN) */
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#define rAUDVOL NR50_REG /**< Sound Master Volume, NR50: Volume and Cart external sound input (VIN) */
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#define AUDVOL_VOL_LEFT(x) ((x) << 4) /**< For Sound Master Volume, NR50: Left Volume, Range: 0-7 */
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#define AUDVOL_VOL_RIGHT(x) ((x)) /**< For Sound Master Volume, NR50: Right Volume, Range: 0-7 */
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#define AUDVOL_VIN_LEFT 0b10000000 /**< For Sound Master Volume, NR50: Cart external sound input (VIN) Left bit, 1 = ON, 0 = OFF */
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#define AUDVOL_VIN_RIGHT 0b00001000 /**< For Sound Master Volume, NR50: Cart external sound input (VIN) Right bit, 1 = ON, 0 = OFF */
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__REG NR51_REG; /**< Sound Panning, NR51: Enable/disable left and right output for sound channels */
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#define rAUDTERM NR51_REG /**< Sound Panning, NR51: Enable/disable left and right output for sound channels */
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#define AUDTERM_4_LEFT 0b10000000 /**< For Sound Panning, NR51: Channel 4 Left bit, 1 = ON, 0 = OFF */
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#define AUDTERM_3_LEFT 0b01000000 /**< For Sound Panning, NR51: Channel 3 Left bit, 1 = ON, 0 = OFF */
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#define AUDTERM_2_LEFT 0b00100000 /**< For Sound Panning, NR51: Channel 2 Left bit, 1 = ON, 0 = OFF */
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#define AUDTERM_1_LEFT 0b00010000 /**< For Sound Panning, NR51: Channel 1 Left bit, 1 = ON, 0 = OFF */
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#define AUDTERM_4_RIGHT 0b00001000 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
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#define AUDTERM_3_RIGHT 0b00000100 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
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#define AUDTERM_2_RIGHT 0b00000010 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
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#define AUDTERM_1_RIGHT 0b00000001 /**< For Sound Panning, NR51: Channel 4 Right bit, 1 = ON, 0 = OFF */
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__REG NR52_REG; /**< Sound Master Control, NR52: ON / OFF */
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#define rAUDENA NR52_REG /**< Sound Master Control, NR52: ON / OFF */
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#define AUDENA_ON 0b10000000 /**< For Sound Master Control, NR52: Sound ON */
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#define AUDENA_OFF 0b00000000 /**< For Sound Master Control, NR52: Sound OFF */
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__BYTE_REG AUD3WAVE[16];
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__BYTE_REG PCM_SAMPLE[16];
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__REG LCDC_REG; /**< LCD control */
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#define rLCDC LCDC_REG
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#if defined(__TARGET_ap)
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#define LCDCF_OFF 0b00000000
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#define LCDCF_ON 0b00000001
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#define LCDCF_WIN9800 0b00000000
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#define LCDCF_WIN9C00 0b00000010
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#define LCDCF_WINOFF 0b00000000
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#define LCDCF_WINON 0b00000100
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#define LCDCF_BG8800 0b00000000
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#define LCDCF_BG8000 0b00001000
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#define LCDCF_BG9800 0b00000000
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#define LCDCF_BG9C00 0b00010000
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#define LCDCF_OBJ8 0b00000000
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#define LCDCF_OBJ16 0b00100000
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#define LCDCF_OBJOFF 0b00000000
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#define LCDCF_OBJON 0b01000000
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#define LCDCF_BGOFF 0b00000000
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#define LCDCF_BGON 0b10000000
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#define LCDCF_B_ON 0
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#define LCDCF_B_WIN9C00 1
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#define LCDCF_B_WINON 2
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#define LCDCF_B_BG8000 3
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#define LCDCF_B_BG9C00 4
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#define LCDCF_B_OBJ16 5
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#define LCDCF_B_OBJON 6
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#define LCDCF_B_BGON 7
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#elif defined(__TARGET_duck)
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#define LCDCF_OFF 0b00000000
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#define LCDCF_ON 0b10000000
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#define LCDCF_WIN9800 0b00000000
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#define LCDCF_WIN9C00 0b00001000
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#define LCDCF_WINOFF 0b00000000
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#define LCDCF_WINON 0b00100000
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#define LCDCF_BG8800 0b00000000
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#define LCDCF_BG8000 0b00010000
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#define LCDCF_BG9800 0b00000000
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#define LCDCF_BG9C00 0b00000100
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#define LCDCF_OBJ8 0b00000000
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#define LCDCF_OBJ16 0b00000010
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#define LCDCF_OBJOFF 0b00000000
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#define LCDCF_OBJON 0b00000001
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#define LCDCF_BGOFF 0b00000000
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#define LCDCF_BGON 0b01000000
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#define LCDCF_B_ON 7
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#define LCDCF_B_WIN9C00 3
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#define LCDCF_B_WINON 5
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#define LCDCF_B_BG8000 4
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#define LCDCF_B_BG9C00 2
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#define LCDCF_B_OBJ16 1
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#define LCDCF_B_OBJON 0
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#define LCDCF_B_BGON 6
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#else
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#define LCDCF_OFF 0b00000000 /**< LCD Control: Off */
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#define LCDCF_ON 0b10000000 /**< LCD Control: On */
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#define LCDCF_WIN9800 0b00000000 /**< Window Tile Map: Use 9800 Region */
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#define LCDCF_WIN9C00 0b01000000 /**< Window Tile Map: Use 9C00 Region */
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#define LCDCF_WINOFF 0b00000000 /**< Window Display: Hidden */
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#define LCDCF_WINON 0b00100000 /**< Window Display: Visible */
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#define LCDCF_BG8800 0b00000000 /**< BG & Window Tile Data: Use 8800 Region */
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#define LCDCF_BG8000 0b00010000 /**< BG & Window Tile Data: Use 8000 Region */
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#define LCDCF_BG9800 0b00000000 /**< BG Tile Map: use 9800 Region */
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#define LCDCF_BG9C00 0b00001000 /**< BG Tile Map: use 9C00 Region */
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#define LCDCF_OBJ8 0b00000000 /**< Sprites Size: 8x8 pixels */
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#define LCDCF_OBJ16 0b00000100 /**< Sprites Size: 8x16 pixels */
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#define LCDCF_OBJOFF 0b00000000 /**< Sprites Display: Hidden */
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#define LCDCF_OBJON 0b00000010 /**< Sprites Display: Visible */
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#define LCDCF_BGOFF 0b00000000 /**< Background Display: Hidden */
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#define LCDCF_BGON 0b00000001 /**< Background Display: Visible */
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#define LCDCF_B_ON 7 /**< Bit for LCD On/Off Select */
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#define LCDCF_B_WIN9C00 6 /**< Bit for Window Tile Map Region Select */
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#define LCDCF_B_WINON 5 /**< Bit for Window Display On/Off Control */
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#define LCDCF_B_BG8000 4 /**< Bit for BG & Window Tile Data Region Select */
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#define LCDCF_B_BG9C00 3 /**< Bit for BG Tile Map Region Select */
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#define LCDCF_B_OBJ16 2 /**< Bit for Sprites Size Select */
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#define LCDCF_B_OBJON 1 /**< Bit for Sprites Display Visible/Hidden Select */
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#define LCDCF_B_BGON 0 /**< Bit for Background Display Visible/Hidden Select */
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#endif
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__REG STAT_REG; /**< LCD status */
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#define rSTAT STAT_REG
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#if defined(__TARGET_ap)
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#define STATF_LYC 0b00000010
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#define STATF_MODE10 0b00000100
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#define STATF_MODE01 0b00001000
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#define STATF_MODE00 0b00010000
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#define STATF_LYCF 0b00100000
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#define STATF_HBL 0b00000000
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#define STATF_VBL 0b10000000
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#define STATF_OAM 0b01000000
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#define STATF_LCD 0b11000000
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#define STATF_BUSY 0b01000000
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#define STATF_B_LYC 1
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#define STATF_B_MODE10 2
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#define STATF_B_MODE01 3
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#define STATF_B_MODE00 4
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#define STATF_B_LYCF 5
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#define STATF_B_VBL 7
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#define STATF_B_OAM 6
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#define STATF_B_BUSY 6
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#else
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#define STATF_LYC 0b01000000 /**< STAT Interrupt: LYC=LY Coincidence Source Enable */
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#define STATF_MODE10 0b00100000 /**< STAT Interrupt: Mode 2 OAM Source Enable */
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#define STATF_MODE01 0b00010000 /**< STAT Interrupt: Mode 1 VBlank Source Enable */
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#define STATF_MODE00 0b00001000 /**< STAT Interrupt: Mode 0 HBlank Source Enable */
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#define STATF_LYCF 0b00000100 /**< LYC=LY Coincidence Status Flag, Set when LY contains the same value as LYC */
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#define STATF_HBL 0b00000000 /**< Current LCD Mode is: 0, in H-Blank */
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#define STATF_VBL 0b00000001 /**< Current LCD Mode is: 1, in V-Blank */
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#define STATF_OAM 0b00000010 /**< Current LCD Mode is: 2, in OAM-RAM is used by system (Searching OAM) */
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#define STATF_LCD 0b00000011 /**< Current LCD Mode is: 3, both OAM and VRAM used by system (Transferring Data to LCD Controller) */
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#define STATF_BUSY 0b00000010 /**< When set, VRAM access is unsafe */
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#define STATF_B_LYC 6 /**< Bit for STAT Interrupt: LYC=LY Coincidence Source Enable */
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#define STATF_B_MODE10 5 /**< Bit for STAT Interrupt: Mode 2 OAM Source Enable */
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#define STATF_B_MODE01 4 /**< Bit for STAT Interrupt: Mode 1 VBlank Source Enable */
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#define STATF_B_MODE00 3 /**< Bit for STAT Interrupt: Mode 0 HBlank Source Enable */
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#define STATF_B_LYCF 2 /**< Bit for LYC=LY Coincidence Status Flag */
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#define STATF_B_VBL 0 /**< */
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#define STATF_B_OAM 1 /**< */
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#define STATF_B_BUSY 1 /**< Bit for when VRAM access is unsafe */
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#endif
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__REG SCY_REG; /**< Scroll Y */
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#define rSCY
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__REG SCX_REG; /**< Scroll X */
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#define rSCX SCX_REG
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__REG LY_REG; /**< LCDC Y-coordinate */
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#define rLY LY_REG
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__REG LYC_REG; /**< LY compare */
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#define rLYC LYC_REG
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__REG DMA_REG; /**< DMA transfer */
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#define rDMA DMA_REG
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__REG BGP_REG; /**< Set and Read the Background palette. \n \n Example with the DMG_PALETTE() helper function and constants: \n BGP_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
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#define rBGP BGP_REG
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__REG OBP0_REG; /**< Set and Read the OBJ (Sprite) palette 0. \n \n The first color entry is always transparent. \n \n Example with the DMG_PALETTE() helper function and constants: \n OBP0_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
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#define rOBP0 OBP0_REG
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__REG OBP1_REG; /**< Set and Read the OBJ (Sprite) palette 1. \n \n The first color entry is always transparent. \n \n Example with the DMG_PALETTE() helper function and constants: \n OBP1_REG = DMG_PALETTE(DMG_BLACK, DMG_DARK_GRAY, DMG_LITE_GRAY, DMG_WHITE); */
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#define rOBP1 OBP1_REG
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__REG WY_REG; /**< Window Y coordinate */
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#define rWY WY_REG
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__REG WX_REG; /**< Window X coordinate */
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#define rWX WX_REG
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__REG KEY1_REG; /**< CPU speed */
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#define rKEY1 KEY1_REG
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#define rSPD KEY1_REG
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#define KEY1F_DBLSPEED 0b10000000
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#define KEY1F_PREPARE 0b00000001
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__REG VBK_REG; /**< VRAM bank select (CGB only) @see VBK_BANK_0, VBK_TILES, VBK_BANK_1, VBK_ATTRIBUTES */
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#define rVBK VBK_REG
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#define VBK_BANK_0 0 /**< Select Regular Map and Normal Tiles (CGB Mode Only) */
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#define VBK_TILES 0 /**< Select Regular Map and Normal Tiles (CGB Mode Only) */
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#define VBK_BANK_1 1 /**< Select Map Attributes and Extra Tile Bank (CGB Mode Only)*/
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#define VBK_ATTRIBUTES 1 /**< Select Map Attributes and Extra Tile Bank (CGB Mode Only) */
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#define BKGF_PRI 0b10000000 /**< Background CGB BG and Window over Sprite priority Enabled */
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#define BKGF_YFLIP 0b01000000 /**< Background CGB Y axis flip: Vertically mirrored */
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#define BKGF_XFLIP 0b00100000 /**< Background CGB X axis flip: Horizontally mirrored */
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#define BKGF_BANK0 0b00000000 /**< Background CGB Tile VRAM-Bank: Use Bank 0 (CGB Mode Only) */
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#define BKGF_BANK1 0b00001000 /**< Background CGB Tile VRAM-Bank: Use Bank 1 (CGB Mode Only) */
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#define BKGF_CGB_PAL0 0b00000000 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL1 0b00000001 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL2 0b00000010 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL3 0b00000011 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL4 0b00000100 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL5 0b00000101 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL6 0b00000110 /**< Background CGB Palette number (CGB Mode Only) */
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#define BKGF_CGB_PAL7 0b00000111 /**< Background CGB Palette number (CGB Mode Only) */
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__REG HDMA1_REG; /**< DMA control 1 */
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#define rHDMA1 HDMA1_REG
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__REG HDMA2_REG; /**< DMA control 2 */
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#define rHDMA2 HDMA2_REG
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__REG HDMA3_REG; /**< DMA control 3 */
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#define rHDMA3 HDMA3_REG
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__REG HDMA4_REG; /**< DMA control 4 */
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#define rHDMA4 HDMA4_REG
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__REG HDMA5_REG; /**< DMA control 5 */
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#define rHDMA5 HDMA5_REG
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#define HDMA5F_MODE_GP 0b00000000
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#define HDMA5F_MODE_HBL 0b10000000
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#define HDMA5F_BUSY 0b10000000
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__REG RP_REG; /**< IR port */
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#define rRP RP_REG
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#define RPF_ENREAD 0b11000000
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#define RPF_DATAIN 0b00000010
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#define RPF_WRITE_HI 0b00000001
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#define RPF_WRITE_LO 0b00000000
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__REG BCPS_REG; /**< BG color palette specification */
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#define rBCPS BCPS_REG
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#define BCPSF_AUTOINC 0b10000000
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__REG BCPD_REG; /**< BG color palette data */
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#define rBCPD BCPD_REG
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__REG OCPS_REG; /**< OBJ color palette specification */
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#define rOCPS OCPS_REG
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#define OCPSF_AUTOINC 0b10000000
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__REG OCPD_REG; /**< OBJ color palette data */
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#define rOCPD OCPD_REG
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__REG SVBK_REG; /**< Selects the WRAM upper region bank (CGB Only). WRAM Banking is NOT officially supported in GBDK and SDCC. The stack must be moved and other special care taken. */
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#define rSVBK SVBK_REG
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#define rSMBK SVBK_REG
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__REG PCM12_REG; /**< Sound channel 1&2 PCM amplitude (R) */
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#define rPCM12 PCM12_REG
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__REG PCM34_REG; /**< Sound channel 3&4 PCM amplitude (R) */
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#define rPCM34 PCM34_REG
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__REG IE_REG; /**< Interrupt enable */
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#define rIE IE_REG
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#define IEF_HILO 0b00010000 /**< Joypad interrupt enable flag */
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#define IEF_SERIAL 0b00001000 /**< Serial interrupt enable flag */
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#define IEF_TIMER 0b00000100 /**< Timer interrupt enable flag */
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#define IEF_STAT 0b00000010 /**< Stat interrupt enable flag */
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#define IEF_VBLANK 0b00000001 /**< VBlank interrupt enable flag */
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/* Square wave duty cycle */
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#define AUDLEN_DUTY_12_5 0b00000000
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#define AUDLEN_DUTY_25 0b01000000
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#define AUDLEN_DUTY_50 0b10000000
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#define AUDLEN_DUTY_75 0b11000000
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#define AUDLEN_LENGTH(x) (x)
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/* Audio envelope flags */
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#define AUDENV_VOL(x) ((x) << 4)
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#define AUDENV_UP 0b00001000
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#define AUDENV_DOWN 0b00000000
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#define AUDENV_LENGTH(x) (x)
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/* Audio trigger flags */
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#define AUDHIGH_RESTART 0b10000000
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#define AUDHIGH_LENGTH_ON 0b01000000
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#define AUDHIGH_LENGTH_OFF 0b00000000
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/* OAM attributes flags */
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#define OAMF_PRI 0b10000000 /**< BG and Window over Sprite Enabled */
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#define OAMF_YFLIP 0b01000000 /**< Sprite Y axis flip: Vertically mirrored */
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#define OAMF_XFLIP 0b00100000 /**< Sprite X axis flip: Horizontally mirrored */
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#define OAMF_PAL0 0b00000000 /**< Sprite Palette number: use OBP0 (Non-CGB Mode Only) */
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#define OAMF_PAL1 0b00010000 /**< Sprite Palette number: use OBP1 (Non-CGB Mode Only) */
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#define OAMF_BANK0 0b00000000 /**< Sprite Tile VRAM-Bank: Use Bank 0 (CGB Mode Only) */
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#define OAMF_BANK1 0b00001000 /**< Sprite Tile VRAM-Bank: Use Bank 1 (CGB Mode Only) */
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#define OAMF_CGB_PAL0 0b00000000 /**< Sprite CGB Palette number: use OCP0 (CGB Mode Only) */
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#define OAMF_CGB_PAL1 0b00000001 /**< Sprite CGB Palette number: use OCP1 (CGB Mode Only) */
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#define OAMF_CGB_PAL2 0b00000010 /**< Sprite CGB Palette number: use OCP2 (CGB Mode Only) */
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#define OAMF_CGB_PAL3 0b00000011 /**< Sprite CGB Palette number: use OCP3 (CGB Mode Only) */
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#define OAMF_CGB_PAL4 0b00000100 /**< Sprite CGB Palette number: use OCP4 (CGB Mode Only) */
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#define OAMF_CGB_PAL5 0b00000101 /**< Sprite CGB Palette number: use OCP5 (CGB Mode Only) */
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#define OAMF_CGB_PAL6 0b00000110 /**< Sprite CGB Palette number: use OCP6 (CGB Mode Only) */
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#define OAMF_CGB_PAL7 0b00000111 /**< Sprite CGB Palette number: use OCP7 (CGB Mode Only) */
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#define OAMF_PALMASK 0b00000111 /**< Mask for Sprite CGB Palette number (CGB Mode Only) */
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#define DEVICE_SCREEN_X_OFFSET 0 /**< Offset of visible screen (in tile units) from left edge of hardware map */
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#define DEVICE_SCREEN_Y_OFFSET 0 /**< Offset of visible screen (in tile units) from top edge of hardware map */
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#define DEVICE_SCREEN_WIDTH 20 /**< Width of visible screen in tile units */
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#define DEVICE_SCREEN_HEIGHT 18 /**< Height of visible screen in tile units */
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#define DEVICE_SCREEN_BUFFER_WIDTH 32 /**< Width of hardware map buffer in tile units */
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#define DEVICE_SCREEN_BUFFER_HEIGHT 32 /**< Height of hardware map buffer in tile units */
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#define DEVICE_SCREEN_MAP_ENTRY_SIZE 1 /**< Number of bytes per hardware map entry */
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#define DEVICE_SPRITE_PX_OFFSET_X 8 /**< Offset of sprite X coordinate origin (in pixels) from left edge of visible screen */
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#define DEVICE_SPRITE_PX_OFFSET_Y 16 /**< Offset of sprite Y coordinate origin (in pixels) from top edge of visible screen */
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#define DEVICE_WINDOW_PX_OFFSET_X 7 /**< Minimal X coordinate of the window layer */
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#define DEVICE_WINDOW_PX_OFFSET_Y 0 /**< Minimal Y coordinate of the window layer */
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#define DEVICE_SCREEN_PX_WIDTH (DEVICE_SCREEN_WIDTH * 8) /**< Width of visible screen in pixels */
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#define DEVICE_SCREEN_PX_HEIGHT (DEVICE_SCREEN_HEIGHT * 8) /**< Height of visible screen in pixels */
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#endif
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