
optiboot_atmega328.elf:     filformat elf32-avr

Sektioner:
Idx Navn          Størrelse   VMA       LMA       Filoffs   Just
  0 .data         00000000  00800100  00007ff4  00000468  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  1 .text         000003f4  00007c00  00007c00  00000074  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .version      00000002  00007ffe  00007ffe  00000468  2**0
                  CONTENTS, READONLY
  3 .stab         000011c4  00000000  00000000  0000046c  2**2
                  CONTENTS, READONLY, DEBUGGING
  4 .stabstr      00000ddc  00000000  00000000  00001630  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .comment      00000027  00000000  00000000  0000240c  2**0
                  CONTENTS, READONLY

Disassemblering af sektion .text:

00007c00 <main>:
    7c00:	1f 92       	push	r1
    7c02:	cd b7       	in	r28, 0x3d	; 61
    7c04:	de b7       	in	r29, 0x3e	; 62
    7c06:	11 24       	eor	r1, r1
    7c08:	84 b7       	in	r24, 0x34	; 52
    7c0a:	14 be       	out	0x34, r1	; 52
    7c0c:	81 fd       	sbrc	r24, 1
    7c0e:	06 c0       	rjmp	.+12     	; 0x7c1c <main+0x1c>
    7c10:	83 ff       	sbrs	r24, 3
    7c12:	03 c0       	rjmp	.+6      	; 0x7c1a <main+0x1a>
    7c14:	89 83       	std	Y+1, r24	; 0x01
    7c16:	f4 d0       	rcall	.+488    	; 0x7e00 <CheckFlashImage>
    7c18:	89 81       	ldd	r24, Y+1	; 0x01
    7c1a:	e3 d1       	rcall	.+966    	; 0x7fe2 <appStart>
    7c1c:	85 e0       	ldi	r24, 0x05	; 5
    7c1e:	80 93 81 00 	sts	0x0081, r24
    7c22:	82 e0       	ldi	r24, 0x02	; 2
    7c24:	80 93 c0 00 	sts	0x00C0, r24
    7c28:	88 e1       	ldi	r24, 0x18	; 24
    7c2a:	80 93 c1 00 	sts	0x00C1, r24
    7c2e:	96 e0       	ldi	r25, 0x06	; 6
    7c30:	90 93 c2 00 	sts	0x00C2, r25
    7c34:	90 e1       	ldi	r25, 0x10	; 16
    7c36:	90 93 c4 00 	sts	0x00C4, r25
    7c3a:	80 93 60 00 	sts	0x0060, r24
    7c3e:	8e e0       	ldi	r24, 0x0E	; 14
    7c40:	80 93 60 00 	sts	0x0060, r24
    7c44:	3b 9a       	sbi	0x07, 3	; 7
    7c46:	86 e0       	ldi	r24, 0x06	; 6
    7c48:	28 e1       	ldi	r18, 0x18	; 24
    7c4a:	3e ef       	ldi	r19, 0xFE	; 254
    7c4c:	91 e0       	ldi	r25, 0x01	; 1
    7c4e:	30 93 85 00 	sts	0x0085, r19
    7c52:	20 93 84 00 	sts	0x0084, r18
    7c56:	96 bb       	out	0x16, r25	; 22
    7c58:	b0 9b       	sbis	0x16, 0	; 22
    7c5a:	fe cf       	rjmp	.-4      	; 0x7c58 <main+0x58>
    7c5c:	33 9a       	sbi	0x06, 3	; 6
    7c5e:	a8 95       	wdr
    7c60:	81 50       	subi	r24, 0x01	; 1
    7c62:	a9 f7       	brne	.-22     	; 0x7c4e <main+0x4e>
    7c64:	61 2c       	mov	r6, r1
    7c66:	71 2c       	mov	r7, r1
    7c68:	08 e1       	ldi	r16, 0x18	; 24
    7c6a:	28 e0       	ldi	r18, 0x08	; 8
    7c6c:	f2 2e       	mov	r15, r18
    7c6e:	ee 24       	eor	r14, r14
    7c70:	e3 94       	inc	r14
    7c72:	35 e0       	ldi	r19, 0x05	; 5
    7c74:	d3 2e       	mov	r13, r19
    7c76:	41 e1       	ldi	r20, 0x11	; 17
    7c78:	c4 2e       	mov	r12, r20
    7c7a:	13 e0       	ldi	r17, 0x03	; 3
    7c7c:	8b d1       	rcall	.+790    	; 0x7f94 <getch>
    7c7e:	81 34       	cpi	r24, 0x41	; 65
    7c80:	69 f4       	brne	.+26     	; 0x7c9c <main+0x9c>
    7c82:	88 d1       	rcall	.+784    	; 0x7f94 <getch>
    7c84:	89 83       	std	Y+1, r24	; 0x01
    7c86:	94 d1       	rcall	.+808    	; 0x7fb0 <verifySpace>
    7c88:	89 81       	ldd	r24, Y+1	; 0x01
    7c8a:	82 38       	cpi	r24, 0x82	; 130
    7c8c:	f9 f0       	breq	.+62     	; 0x7ccc <main+0xcc>
    7c8e:	81 38       	cpi	r24, 0x81	; 129
    7c90:	11 f4       	brne	.+4      	; 0x7c96 <main+0x96>
    7c92:	85 e0       	ldi	r24, 0x05	; 5
    7c94:	01 c0       	rjmp	.+2      	; 0x7c98 <main+0x98>
    7c96:	83 e0       	ldi	r24, 0x03	; 3
    7c98:	76 d1       	rcall	.+748    	; 0x7f86 <putch>
    7c9a:	7b c0       	rjmp	.+246    	; 0x7d92 <main+0x192>
    7c9c:	82 34       	cpi	r24, 0x42	; 66
    7c9e:	11 f4       	brne	.+4      	; 0x7ca4 <main+0xa4>
    7ca0:	84 e1       	ldi	r24, 0x14	; 20
    7ca2:	03 c0       	rjmp	.+6      	; 0x7caa <main+0xaa>
    7ca4:	85 34       	cpi	r24, 0x45	; 69
    7ca6:	19 f4       	brne	.+6      	; 0x7cae <main+0xae>
    7ca8:	85 e0       	ldi	r24, 0x05	; 5
    7caa:	8e d1       	rcall	.+796    	; 0x7fc8 <getNch>
    7cac:	72 c0       	rjmp	.+228    	; 0x7d92 <main+0x192>
    7cae:	85 35       	cpi	r24, 0x55	; 85
    7cb0:	49 f4       	brne	.+18     	; 0x7cc4 <main+0xc4>
    7cb2:	70 d1       	rcall	.+736    	; 0x7f94 <getch>
    7cb4:	b8 2e       	mov	r11, r24
    7cb6:	6e d1       	rcall	.+732    	; 0x7f94 <getch>
    7cb8:	6b 2c       	mov	r6, r11
    7cba:	71 2c       	mov	r7, r1
    7cbc:	78 2a       	or	r7, r24
    7cbe:	66 0c       	add	r6, r6
    7cc0:	77 1c       	adc	r7, r7
    7cc2:	66 c0       	rjmp	.+204    	; 0x7d90 <main+0x190>
    7cc4:	86 35       	cpi	r24, 0x56	; 86
    7cc6:	21 f4       	brne	.+8      	; 0x7cd0 <main+0xd0>
    7cc8:	84 e0       	ldi	r24, 0x04	; 4
    7cca:	7e d1       	rcall	.+764    	; 0x7fc8 <getNch>
    7ccc:	80 e0       	ldi	r24, 0x00	; 0
    7cce:	e4 cf       	rjmp	.-56     	; 0x7c98 <main+0x98>
    7cd0:	84 36       	cpi	r24, 0x64	; 100
    7cd2:	09 f0       	breq	.+2      	; 0x7cd6 <main+0xd6>
    7cd4:	3f c0       	rjmp	.+126    	; 0x7d54 <main+0x154>
    7cd6:	5e d1       	rcall	.+700    	; 0x7f94 <getch>
    7cd8:	5d d1       	rcall	.+698    	; 0x7f94 <getch>
    7cda:	98 2e       	mov	r9, r24
    7cdc:	5b d1       	rcall	.+694    	; 0x7f94 <getch>
    7cde:	61 14       	cp	r6, r1
    7ce0:	80 e7       	ldi	r24, 0x70	; 112
    7ce2:	78 06       	cpc	r7, r24
    7ce4:	18 f4       	brcc	.+6      	; 0x7cec <main+0xec>
    7ce6:	f3 01       	movw	r30, r6
    7ce8:	17 bf       	out	0x37, r17	; 55
    7cea:	e8 95       	spm
    7cec:	a1 2c       	mov	r10, r1
    7cee:	bb 24       	eor	r11, r11
    7cf0:	b3 94       	inc	r11
    7cf2:	50 d1       	rcall	.+672    	; 0x7f94 <getch>
    7cf4:	f5 01       	movw	r30, r10
    7cf6:	81 93       	st	Z+, r24
    7cf8:	5f 01       	movw	r10, r30
    7cfa:	9e 12       	cpse	r9, r30
    7cfc:	fa cf       	rjmp	.-12     	; 0x7cf2 <main+0xf2>
    7cfe:	61 14       	cp	r6, r1
    7d00:	f0 e7       	ldi	r31, 0x70	; 112
    7d02:	7f 06       	cpc	r7, r31
    7d04:	18 f0       	brcs	.+6      	; 0x7d0c <main+0x10c>
    7d06:	f3 01       	movw	r30, r6
    7d08:	17 bf       	out	0x37, r17	; 55
    7d0a:	e8 95       	spm
    7d0c:	51 d1       	rcall	.+674    	; 0x7fb0 <verifySpace>
    7d0e:	07 b6       	in	r0, 0x37	; 55
    7d10:	00 fc       	sbrc	r0, 0
    7d12:	fd cf       	rjmp	.-6      	; 0x7d0e <main+0x10e>
    7d14:	a3 01       	movw	r20, r6
    7d16:	a0 e0       	ldi	r26, 0x00	; 0
    7d18:	b1 e0       	ldi	r27, 0x01	; 1
    7d1a:	8c 91       	ld	r24, X
    7d1c:	12 96       	adiw	r26, 0x02	; 2
    7d1e:	9d 01       	movw	r18, r26
    7d20:	21 50       	subi	r18, 0x01	; 1
    7d22:	31 09       	sbc	r19, r1
    7d24:	f9 01       	movw	r30, r18
    7d26:	20 81       	ld	r18, Z
    7d28:	90 e0       	ldi	r25, 0x00	; 0
    7d2a:	92 2b       	or	r25, r18
    7d2c:	fa 01       	movw	r30, r20
    7d2e:	0c 01       	movw	r0, r24
    7d30:	e7 be       	out	0x37, r14	; 55
    7d32:	e8 95       	spm
    7d34:	11 24       	eor	r1, r1
    7d36:	4e 5f       	subi	r20, 0xFE	; 254
    7d38:	5f 4f       	sbci	r21, 0xFF	; 255
    7d3a:	a0 38       	cpi	r26, 0x80	; 128
    7d3c:	f1 e0       	ldi	r31, 0x01	; 1
    7d3e:	bf 07       	cpc	r27, r31
    7d40:	61 f7       	brne	.-40     	; 0x7d1a <main+0x11a>
    7d42:	f3 01       	movw	r30, r6
    7d44:	d7 be       	out	0x37, r13	; 55
    7d46:	e8 95       	spm
    7d48:	07 b6       	in	r0, 0x37	; 55
    7d4a:	00 fc       	sbrc	r0, 0
    7d4c:	fd cf       	rjmp	.-6      	; 0x7d48 <main+0x148>
    7d4e:	c7 be       	out	0x37, r12	; 55
    7d50:	e8 95       	spm
    7d52:	1f c0       	rjmp	.+62     	; 0x7d92 <main+0x192>
    7d54:	84 37       	cpi	r24, 0x74	; 116
    7d56:	69 f4       	brne	.+26     	; 0x7d72 <main+0x172>
    7d58:	1d d1       	rcall	.+570    	; 0x7f94 <getch>
    7d5a:	1c d1       	rcall	.+568    	; 0x7f94 <getch>
    7d5c:	b8 2e       	mov	r11, r24
    7d5e:	1a d1       	rcall	.+564    	; 0x7f94 <getch>
    7d60:	27 d1       	rcall	.+590    	; 0x7fb0 <verifySpace>
    7d62:	f3 01       	movw	r30, r6
    7d64:	85 91       	lpm	r24, Z+
    7d66:	3f 01       	movw	r6, r30
    7d68:	0e d1       	rcall	.+540    	; 0x7f86 <putch>
    7d6a:	ba 94       	dec	r11
    7d6c:	b1 10       	cpse	r11, r1
    7d6e:	f9 cf       	rjmp	.-14     	; 0x7d62 <main+0x162>
    7d70:	10 c0       	rjmp	.+32     	; 0x7d92 <main+0x192>
    7d72:	85 37       	cpi	r24, 0x75	; 117
    7d74:	39 f4       	brne	.+14     	; 0x7d84 <main+0x184>
    7d76:	1c d1       	rcall	.+568    	; 0x7fb0 <verifySpace>
    7d78:	8e e1       	ldi	r24, 0x1E	; 30
    7d7a:	05 d1       	rcall	.+522    	; 0x7f86 <putch>
    7d7c:	85 e9       	ldi	r24, 0x95	; 149
    7d7e:	03 d1       	rcall	.+518    	; 0x7f86 <putch>
    7d80:	8f e0       	ldi	r24, 0x0F	; 15
    7d82:	8a cf       	rjmp	.-236    	; 0x7c98 <main+0x98>
    7d84:	81 35       	cpi	r24, 0x51	; 81
    7d86:	21 f4       	brne	.+8      	; 0x7d90 <main+0x190>
    7d88:	00 93 60 00 	sts	0x0060, r16
    7d8c:	f0 92 60 00 	sts	0x0060, r15
    7d90:	0f d1       	rcall	.+542    	; 0x7fb0 <verifySpace>
    7d92:	80 e1       	ldi	r24, 0x10	; 16
    7d94:	f8 d0       	rcall	.+496    	; 0x7f86 <putch>
    7d96:	72 cf       	rjmp	.-284    	; 0x7c7c <main+0x7c>

00007d98 <SPI_transfer>:
#define SPIFLASH_JEDECID          0x9F        // read JEDEC ID
//#define DEBUG_ON                            // uncomment to enable Serial debugging 
                                              // (will output different characters depending on which path the bootloader takes)

uint8_t SPI_transfer(uint8_t _data) {
  SPDR = _data;
    7d98:	8e bd       	out	0x2e, r24	; 46
  while (!(SPSR & _BV(SPIF)));
    7d9a:	0d b4       	in	r0, 0x2d	; 45
    7d9c:	07 fe       	sbrs	r0, 7
    7d9e:	fd cf       	rjmp	.-6      	; 0x7d9a <SPI_transfer+0x2>
  return SPDR;
    7da0:	8e b5       	in	r24, 0x2e	; 46
}
    7da2:	08 95       	ret

00007da4 <FLASH_busy>:

uint8_t FLASH_busy()
{
  FLASH_SELECT;
    7da4:	28 98       	cbi	0x05, 0	; 5
  SPI_transfer(SPIFLASH_STATUSREAD);
    7da6:	85 e0       	ldi	r24, 0x05	; 5
    7da8:	f7 df       	rcall	.-18     	; 0x7d98 <SPI_transfer>
    7daa:	80 e0       	ldi	r24, 0x00	; 0
  uint8_t status = SPI_transfer(0);
    7dac:	f5 df       	rcall	.-22     	; 0x7d98 <SPI_transfer>
    7dae:	28 9a       	sbi	0x05, 0	; 5
    7db0:	81 70       	andi	r24, 0x01	; 1
  FLASH_UNSELECT;
    7db2:	08 95       	ret

00007db4 <FLASH_command>:
  return status & 1;
}

void FLASH_command(uint8_t cmd, uint8_t isWrite){
    7db4:	cf 93       	push	r28
    7db6:	c8 2f       	mov	r28, r24
  if (isWrite)
    7db8:	66 23       	and	r22, r22
    7dba:	21 f0       	breq	.+8      	; 0x7dc4 <FLASH_command+0x10>
  {
    FLASH_command(SPIFLASH_WRITEENABLE, 0); // Write Enable
    7dbc:	60 e0       	ldi	r22, 0x00	; 0
    7dbe:	86 e0       	ldi	r24, 0x06	; 6
    7dc0:	f9 df       	rcall	.-14     	; 0x7db4 <FLASH_command>
    7dc2:	28 9a       	sbi	0x05, 0	; 5
    FLASH_UNSELECT;
    7dc4:	ef df       	rcall	.-34     	; 0x7da4 <FLASH_busy>
  }
  while(FLASH_busy()); //wait for chip to become available
    7dc6:	81 11       	cpse	r24, r1
    7dc8:	fd cf       	rjmp	.-6      	; 0x7dc4 <FLASH_command+0x10>
    7dca:	28 98       	cbi	0x05, 0	; 5
    7dcc:	8c 2f       	mov	r24, r28
  FLASH_SELECT;
    7dce:	cf 91       	pop	r28
  SPI_transfer(cmd);
    7dd0:	e3 cf       	rjmp	.-58     	; 0x7d98 <SPI_transfer>

00007dd2 <FLASH_readByte>:
}

uint8_t FLASH_readByte(uint32_t addr) {
    7dd2:	cf 92       	push	r12
    7dd4:	df 92       	push	r13
    7dd6:	ef 92       	push	r14
    7dd8:	ff 92       	push	r15
    7dda:	6b 01       	movw	r12, r22
    7ddc:	7c 01       	movw	r14, r24
  FLASH_command(SPIFLASH_ARRAYREADLOWFREQ, 0);
    7dde:	60 e0       	ldi	r22, 0x00	; 0
    7de0:	83 e0       	ldi	r24, 0x03	; 3
    7de2:	e8 df       	rcall	.-48     	; 0x7db4 <FLASH_command>
    7de4:	8e 2d       	mov	r24, r14
  SPI_transfer(addr >> 16);
    7de6:	d8 df       	rcall	.-80     	; 0x7d98 <SPI_transfer>
    7de8:	8d 2d       	mov	r24, r13
    7dea:	d6 df       	rcall	.-84     	; 0x7d98 <SPI_transfer>
  SPI_transfer(addr >> 8);
    7dec:	8c 2d       	mov	r24, r12
    7dee:	d4 df       	rcall	.-88     	; 0x7d98 <SPI_transfer>
    7df0:	80 e0       	ldi	r24, 0x00	; 0
  SPI_transfer(addr);
    7df2:	d2 df       	rcall	.-92     	; 0x7d98 <SPI_transfer>
    7df4:	28 9a       	sbi	0x05, 0	; 5
    7df6:	ff 90       	pop	r15
  //SPI.transfer(0); //"dont care", needed with SPIFLASH_ARRAYREAD command only
  uint8_t result = SPI_transfer(0);
    7df8:	ef 90       	pop	r14
    7dfa:	df 90       	pop	r13
    7dfc:	cf 90       	pop	r12
  FLASH_UNSELECT;
    7dfe:	08 95       	ret

00007e00 <CheckFlashImage>:
  return result;
}

void CheckFlashImage() {
    7e00:	9f 92       	push	r9
    7e02:	af 92       	push	r10
    7e04:	bf 92       	push	r11
    7e06:	cf 92       	push	r12
    7e08:	df 92       	push	r13
    7e0a:	ef 92       	push	r14
    7e0c:	ff 92       	push	r15
    7e0e:	0f 93       	push	r16
    7e10:	1f 93       	push	r17
    7e12:	cf 93       	push	r28
    7e14:	df 93       	push	r29
    "wdr\n"
  );
}

void watchdogConfig(uint8_t x) {
  WDTCSR = _BV(WDCE) | _BV(WDE);
    7e16:	88 e1       	ldi	r24, 0x18	; 24
    7e18:	80 93 60 00 	sts	0x0060, r24
  WDTCSR = x;
    7e1c:	10 92 60 00 	sts	0x0060, r1
#endif
  watchdogConfig(WATCHDOG_OFF);

  //SPI INIT
#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega88) || defined(__AVR_ATmega8__) || defined(__AVR_ATmega88__)
  DDRB |= _BV(FLASHSS) | _BV(SS) | _BV(PB3) | _BV(PB5); //OUTPUTS for FLASH_SS and SS, MOSI, SCK
    7e20:	84 b1       	in	r24, 0x04	; 4
    7e22:	8d 62       	ori	r24, 0x2D	; 45
    7e24:	84 b9       	out	0x04, r24	; 4
  FLASH_UNSELECT; //unselect FLASH chip
    7e26:	28 9a       	sbi	0x05, 0	; 5
  PORTB |= _BV(SS); //set SS HIGH
    7e28:	2a 9a       	sbi	0x05, 2	; 5
  //SPCR = (SPCR & ~SPI_MODE_MASK) | SPI_MODE0 ; //SPI MODE 0
  //SPCR = (SPCR & ~SPI_CLOCK_MASK) | (SPI_CLOCK_DIV2 & SPI_CLOCK_MASK); //clock divider = 2
  //SPSR = (SPSR & ~SPI_2XCLOCK_MASK) | ((SPI_CLOCK_DIV2 >> 2) & SPI_2XCLOCK_MASK);

  // Warning: if the SS pin ever becomes a LOW INPUT then SPI automatically switches to Slave, so the data direction of the SS pin MUST be kept as OUTPUT.
  SPCR |= _BV(MSTR) | _BV(SPE); //enable SPI and set SPI to MASTER mode
    7e2a:	8c b5       	in	r24, 0x2c	; 44
    7e2c:	80 65       	ori	r24, 0x50	; 80
    7e2e:	8c bd       	out	0x2c, r24	; 44

  //read first byte of JEDECID, if chip is present it should return a non-0 and non-FF value
  FLASH_SELECT;
    7e30:	28 98       	cbi	0x05, 0	; 5
  SPI_transfer(SPIFLASH_JEDECID);
    7e32:	8f e9       	ldi	r24, 0x9F	; 159
    7e34:	b1 df       	rcall	.-158    	; 0x7d98 <SPI_transfer>
    7e36:	80 e0       	ldi	r24, 0x00	; 0
  uint8_t deviceId = SPI_transfer(0);
    7e38:	af df       	rcall	.-162    	; 0x7d98 <SPI_transfer>
    7e3a:	28 9a       	sbi	0x05, 0	; 5
    7e3c:	81 50       	subi	r24, 0x01	; 1
  FLASH_UNSELECT;
    7e3e:	8e 3f       	cpi	r24, 0xFE	; 254
  if (deviceId==0 || deviceId==0xFF) return;
    7e40:	08 f0       	brcs	.+2      	; 0x7e44 <CheckFlashImage+0x44>
    7e42:	95 c0       	rjmp	.+298    	; 0x7f6e <CheckFlashImage+0x16e>
    7e44:	61 e0       	ldi	r22, 0x01	; 1
    7e46:	81 e0       	ldi	r24, 0x01	; 1
  
  //global unprotect  
  FLASH_command(SPIFLASH_STATUSWRITE, 1);
    7e48:	b5 df       	rcall	.-150    	; 0x7db4 <FLASH_command>
    7e4a:	80 e0       	ldi	r24, 0x00	; 0
    7e4c:	a5 df       	rcall	.-182    	; 0x7d98 <SPI_transfer>
    7e4e:	28 9a       	sbi	0x05, 0	; 5
  SPI_transfer(0);
    7e50:	60 e0       	ldi	r22, 0x00	; 0
    7e52:	70 e0       	ldi	r23, 0x00	; 0
    7e54:	cb 01       	movw	r24, r22
  FLASH_UNSELECT;
    7e56:	bd df       	rcall	.-134    	; 0x7dd2 <FLASH_readByte>
  
  //check if any flash image exists on external FLASH chip
  if (FLASH_readByte(0)=='F' && FLASH_readByte(1)=='L' && FLASH_readByte(2)=='X' && FLASH_readByte(6)==':' && FLASH_readByte(9)==':')
    7e58:	86 34       	cpi	r24, 0x46	; 70
    7e5a:	09 f0       	breq	.+2      	; 0x7e5e <CheckFlashImage+0x5e>
    7e5c:	88 c0       	rjmp	.+272    	; 0x7f6e <CheckFlashImage+0x16e>
    7e5e:	61 e0       	ldi	r22, 0x01	; 1
    7e60:	70 e0       	ldi	r23, 0x00	; 0
    7e62:	80 e0       	ldi	r24, 0x00	; 0
    7e64:	90 e0       	ldi	r25, 0x00	; 0
    7e66:	b5 df       	rcall	.-150    	; 0x7dd2 <FLASH_readByte>
    7e68:	8c 34       	cpi	r24, 0x4C	; 76
    7e6a:	09 f0       	breq	.+2      	; 0x7e6e <CheckFlashImage+0x6e>
    7e6c:	80 c0       	rjmp	.+256    	; 0x7f6e <CheckFlashImage+0x16e>
    7e6e:	62 e0       	ldi	r22, 0x02	; 2
    7e70:	70 e0       	ldi	r23, 0x00	; 0
    7e72:	80 e0       	ldi	r24, 0x00	; 0
    7e74:	90 e0       	ldi	r25, 0x00	; 0
    7e76:	ad df       	rcall	.-166    	; 0x7dd2 <FLASH_readByte>
    7e78:	88 35       	cpi	r24, 0x58	; 88
    7e7a:	09 f0       	breq	.+2      	; 0x7e7e <CheckFlashImage+0x7e>
    7e7c:	78 c0       	rjmp	.+240    	; 0x7f6e <CheckFlashImage+0x16e>
    7e7e:	66 e0       	ldi	r22, 0x06	; 6
    7e80:	70 e0       	ldi	r23, 0x00	; 0
    7e82:	80 e0       	ldi	r24, 0x00	; 0
    7e84:	90 e0       	ldi	r25, 0x00	; 0
    7e86:	a5 df       	rcall	.-182    	; 0x7dd2 <FLASH_readByte>
    7e88:	8a 33       	cpi	r24, 0x3A	; 58
    7e8a:	09 f0       	breq	.+2      	; 0x7e8e <CheckFlashImage+0x8e>
    7e8c:	70 c0       	rjmp	.+224    	; 0x7f6e <CheckFlashImage+0x16e>
    7e8e:	69 e0       	ldi	r22, 0x09	; 9
    7e90:	70 e0       	ldi	r23, 0x00	; 0
    7e92:	80 e0       	ldi	r24, 0x00	; 0
    7e94:	90 e0       	ldi	r25, 0x00	; 0
    7e96:	9d df       	rcall	.-198    	; 0x7dd2 <FLASH_readByte>
    7e98:	8a 33       	cpi	r24, 0x3A	; 58
    7e9a:	09 f0       	breq	.+2      	; 0x7e9e <CheckFlashImage+0x9e>
    7e9c:	68 c0       	rjmp	.+208    	; 0x7f6e <CheckFlashImage+0x16e>
    7e9e:	67 e0       	ldi	r22, 0x07	; 7
    7ea0:	70 e0       	ldi	r23, 0x00	; 0
    7ea2:	80 e0       	ldi	r24, 0x00	; 0
    7ea4:	90 e0       	ldi	r25, 0x00	; 0
    7ea6:	95 df       	rcall	.-214    	; 0x7dd2 <FLASH_readByte>
    7ea8:	c8 2f       	mov	r28, r24
    7eaa:	68 e0       	ldi	r22, 0x08	; 8
    7eac:	70 e0       	ldi	r23, 0x00	; 0
    7eae:	80 e0       	ldi	r24, 0x00	; 0
  {
#ifdef DEBUG_ON
    putch('L');
#endif
    
    uint16_t imagesize = (FLASH_readByte(7)<<8) | FLASH_readByte(8);
    7eb0:	90 e0       	ldi	r25, 0x00	; 0
    7eb2:	8f df       	rcall	.-226    	; 0x7dd2 <FLASH_readByte>
    7eb4:	d0 e0       	ldi	r29, 0x00	; 0
    7eb6:	dc 2f       	mov	r29, r28
    7eb8:	cc 27       	eor	r28, r28
    7eba:	c8 2b       	or	r28, r24
    7ebc:	c0 fd       	sbrc	r28, 0
    7ebe:	57 c0       	rjmp	.+174    	; 0x7f6e <CheckFlashImage+0x16e>
    7ec0:	33 9a       	sbi	0x06, 3	; 6
    7ec2:	c1 2c       	mov	r12, r1
    7ec4:	d1 2c       	mov	r13, r1
    7ec6:	00 e0       	ldi	r16, 0x00	; 0
    7ec8:	10 e0       	ldi	r17, 0x00	; 0
    7eca:	bb 24       	eor	r11, r11
    7ecc:	b3 94       	inc	r11
    7ece:	83 e0       	ldi	r24, 0x03	; 3
    7ed0:	a8 2e       	mov	r10, r24
    if (imagesize%2!=0) return; //basic check that we got even # of bytes
    7ed2:	95 e0       	ldi	r25, 0x05	; 5
    7ed4:	99 2e       	mov	r9, r25
    
    uint16_t b, i, nextAddress=0;
    
    LED_PIN |= _BV(LED);
    7ed6:	0c 17       	cp	r16, r28
#endif
    
    uint16_t imagesize = (FLASH_readByte(7)<<8) | FLASH_readByte(8);
    if (imagesize%2!=0) return; //basic check that we got even # of bytes
    
    uint16_t b, i, nextAddress=0;
    7ed8:	1d 07       	cpc	r17, r29
    7eda:	70 f5       	brcc	.+92     	; 0x7f38 <CheckFlashImage+0x138>
    
    LED_PIN |= _BV(LED);
    for (i=0; i<imagesize; i+=2)
    7edc:	b8 01       	movw	r22, r16
    7ede:	66 5f       	subi	r22, 0xF6	; 246
#endif
      
      //read 2 bytes (16 bits) from flash image, transfer them to page buffer
      b = FLASH_readByte(i+10); // flash image starts at position 10 on the external flash memory: FLX:XX:FLASH_IMAGE_BYTES_HERE...... (XX = two size bytes)
      b |= FLASH_readByte(i+11) << 8; //bytes are stored big endian on external flash, need to flip the bytes to little endian for transfer to internal flash
      __boot_page_fill_short((uint16_t)(void*)i,b);
    7ee0:	7f 4f       	sbci	r23, 0xFF	; 255
    7ee2:	80 e0       	ldi	r24, 0x00	; 0

      //when 1 page is full (or we're on the last page), write it to the internal flash memory
      if ((i+2)%SPM_PAGESIZE==0 || (i+2==imagesize))
      {
        __boot_page_erase_short((uint16_t)(void*)nextAddress); //(i+2-SPM_PAGESIZE)
    7ee4:	90 e0       	ldi	r25, 0x00	; 0
    7ee6:	75 df       	rcall	.-278    	; 0x7dd2 <FLASH_readByte>
        boot_spm_busy_wait();
        // Write from programming buffer
        __boot_page_write_short((uint16_t)(void*)nextAddress ); //(i+2-SPM_PAGESIZE)
    7ee8:	e8 2e       	mov	r14, r24
    7eea:	f1 2c       	mov	r15, r1
    if (imagesize%2!=0) return; //basic check that we got even # of bytes
    
    uint16_t b, i, nextAddress=0;
    
    LED_PIN |= _BV(LED);
    for (i=0; i<imagesize; i+=2)
    7eec:	b8 01       	movw	r22, r16
    7eee:	65 5f       	subi	r22, 0xF5	; 245
    7ef0:	7f 4f       	sbci	r23, 0xFF	; 255
    7ef2:	80 e0       	ldi	r24, 0x00	; 0
    7ef4:	90 e0       	ldi	r25, 0x00	; 0
    7ef6:	6d df       	rcall	.-294    	; 0x7dd2 <FLASH_readByte>
#ifdef DEBUG_ON
      putch('*');
#endif
      
      //read 2 bytes (16 bits) from flash image, transfer them to page buffer
      b = FLASH_readByte(i+10); // flash image starts at position 10 on the external flash memory: FLX:XX:FLASH_IMAGE_BYTES_HERE...... (XX = two size bytes)
    7ef8:	f8 2a       	or	r15, r24
    7efa:	f8 01       	movw	r30, r16
    7efc:	07 01       	movw	r0, r14
    7efe:	b7 be       	out	0x37, r11	; 55
    7f00:	e8 95       	spm
    7f02:	11 24       	eor	r1, r1
    7f04:	0e 5f       	subi	r16, 0xFE	; 254
    7f06:	1f 4f       	sbci	r17, 0xFF	; 255
    7f08:	c8 01       	movw	r24, r16
      b |= FLASH_readByte(i+11) << 8; //bytes are stored big endian on external flash, need to flip the bytes to little endian for transfer to internal flash
    7f0a:	8f 77       	andi	r24, 0x7F	; 127
    7f0c:	99 27       	eor	r25, r25
    7f0e:	89 2b       	or	r24, r25
    7f10:	19 f0       	breq	.+6      	; 0x7f18 <CheckFlashImage+0x118>
    7f12:	0c 17       	cp	r16, r28
      __boot_page_fill_short((uint16_t)(void*)i,b);
    7f14:	1d 07       	cpc	r17, r29
    7f16:	f9 f6       	brne	.-66     	; 0x7ed6 <CheckFlashImage+0xd6>
    7f18:	f6 01       	movw	r30, r12
    7f1a:	a7 be       	out	0x37, r10	; 55
    7f1c:	e8 95       	spm

      //when 1 page is full (or we're on the last page), write it to the internal flash memory
      if ((i+2)%SPM_PAGESIZE==0 || (i+2==imagesize))
    7f1e:	07 b6       	in	r0, 0x37	; 55
    7f20:	00 fc       	sbrc	r0, 0
    7f22:	fd cf       	rjmp	.-6      	; 0x7f1e <CheckFlashImage+0x11e>
    7f24:	f6 01       	movw	r30, r12
    7f26:	97 be       	out	0x37, r9	; 55
    7f28:	e8 95       	spm
    7f2a:	07 b6       	in	r0, 0x37	; 55
    7f2c:	00 fc       	sbrc	r0, 0
    7f2e:	fd cf       	rjmp	.-6      	; 0x7f2a <CheckFlashImage+0x12a>
    7f30:	f0 e8       	ldi	r31, 0x80	; 128
      {
        __boot_page_erase_short((uint16_t)(void*)nextAddress); //(i+2-SPM_PAGESIZE)
    7f32:	cf 0e       	add	r12, r31
    7f34:	d1 1c       	adc	r13, r1
    7f36:	cf cf       	rjmp	.-98     	; 0x7ed6 <CheckFlashImage+0xd6>
        boot_spm_busy_wait();
    7f38:	33 98       	cbi	0x06, 3	; 6
    7f3a:	81 e1       	ldi	r24, 0x11	; 17
    7f3c:	87 bf       	out	0x37, r24	; 55
        // Write from programming buffer
        __boot_page_write_short((uint16_t)(void*)nextAddress ); //(i+2-SPM_PAGESIZE)
    7f3e:	e8 95       	spm
    7f40:	2a 96       	adiw	r28, 0x0a	; 10
    7f42:	61 e0       	ldi	r22, 0x01	; 1
        boot_spm_busy_wait();
    7f44:	c1 30       	cpi	r28, 0x01	; 1
    7f46:	d0 48       	sbci	r29, 0x80	; 128
    7f48:	10 f4       	brcc	.+4      	; 0x7f4e <CheckFlashImage+0x14e>
        nextAddress += SPM_PAGESIZE;
    7f4a:	82 e5       	ldi	r24, 0x52	; 82
    7f4c:	01 c0       	rjmp	.+2      	; 0x7f50 <CheckFlashImage+0x150>
    7f4e:	88 ed       	ldi	r24, 0xD8	; 216
    7f50:	31 df       	rcall	.-414    	; 0x7db4 <FLASH_command>
      }
    }
    LED_PIN &= ~_BV(LED);
    7f52:	80 e0       	ldi	r24, 0x00	; 0

#if defined(RWWSRE)
    // Reenable read access to flash
    boot_rww_enable();
    7f54:	21 df       	rcall	.-446    	; 0x7d98 <SPI_transfer>
    7f56:	80 e0       	ldi	r24, 0x00	; 0
    7f58:	1f df       	rcall	.-450    	; 0x7d98 <SPI_transfer>
#ifdef DEBUG_ON
    putch('E');
#endif

    //erase the first 32/64K block where flash image resided (atmega328 should be less than 31K, and atmega1284 can be up to 64K)
    if (imagesize+10<=32768) FLASH_command(SPIFLASH_BLOCKERASE_32K, 1);
    7f5a:	80 e0       	ldi	r24, 0x00	; 0
    7f5c:	1d df       	rcall	.-454    	; 0x7d98 <SPI_transfer>
    7f5e:	28 9a       	sbi	0x05, 0	; 5
    7f60:	88 e1       	ldi	r24, 0x18	; 24
    7f62:	80 93 60 00 	sts	0x0060, r24
    7f66:	88 e0       	ldi	r24, 0x08	; 8
    else FLASH_command(SPIFLASH_BLOCKERASE_64K, 1);
    7f68:	80 93 60 00 	sts	0x0060, r24
    7f6c:	ff cf       	rjmp	.-2      	; 0x7f6c <CheckFlashImage+0x16c>
    SPI_transfer(0);
    7f6e:	df 91       	pop	r29
    7f70:	cf 91       	pop	r28
    7f72:	1f 91       	pop	r17
    SPI_transfer(0);
    7f74:	0f 91       	pop	r16
    7f76:	ff 90       	pop	r15
    7f78:	ef 90       	pop	r14
    SPI_transfer(0);
    7f7a:	df 90       	pop	r13
    7f7c:	cf 90       	pop	r12
    7f7e:	bf 90       	pop	r11
    FLASH_UNSELECT;
    7f80:	af 90       	pop	r10
    "wdr\n"
  );
}

void watchdogConfig(uint8_t x) {
  WDTCSR = _BV(WDCE) | _BV(WDE);
    7f82:	9f 90       	pop	r9
    7f84:	08 95       	ret

00007f86 <putch>:
  }
}

void putch(char ch) {
#ifndef SOFT_UART
  while (!(UART_SRA & _BV(UDRE0)));
    7f86:	90 91 c0 00 	lds	r25, 0x00C0
    7f8a:	95 ff       	sbrs	r25, 5
    7f8c:	fc cf       	rjmp	.-8      	; 0x7f86 <putch>
  UART_UDR = ch;
    7f8e:	80 93 c6 00 	sts	0x00C6, r24
    7f92:	08 95       	ret

00007f94 <getch>:

#ifdef LED_DATA_FLASH
#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
  LED_PORT ^= _BV(LED);
#else
  LED_PIN |= _BV(LED);
    7f94:	33 9a       	sbi	0x06, 3	; 6
      [uartBit] "I" (UART_RX_BIT)
    :
      "r25"
);
#else
  while(!(UART_SRA & _BV(RXC0)))
    7f96:	80 91 c0 00 	lds	r24, 0x00C0
    7f9a:	87 ff       	sbrs	r24, 7
    7f9c:	fc cf       	rjmp	.-8      	; 0x7f96 <getch+0x2>
    ;
  if (!(UART_SRA & _BV(FE0))) {
    7f9e:	80 91 c0 00 	lds	r24, 0x00C0
    7fa2:	84 fd       	sbrc	r24, 4
    7fa4:	01 c0       	rjmp	.+2      	; 0x7fa8 <getch+0x14>
}
#endif

// Watchdog functions. These are only safe with interrupts turned off.
void watchdogReset() {
  __asm__ __volatile__ (
    7fa6:	a8 95       	wdr
       * don't care that an invalid char is returned...)
       */
    watchdogReset();
  }
  
  ch = UART_UDR;
    7fa8:	80 91 c6 00 	lds	r24, 0x00C6

#ifdef LED_DATA_FLASH
#if defined(__AVR_ATmega8__) || defined (__AVR_ATmega32__)
  LED_PORT ^= _BV(LED);
#else
  LED_PIN |= _BV(LED);
    7fac:	33 9a       	sbi	0x06, 3	; 6
#endif
#endif

  return ch;
}
    7fae:	08 95       	ret

00007fb0 <verifySpace>:
  do getch(); while (--count);
  verifySpace();
}

void verifySpace() {
  if (getch() != CRC_EOP) {
    7fb0:	f1 df       	rcall	.-30     	; 0x7f94 <getch>
    7fb2:	80 32       	cpi	r24, 0x20	; 32
    7fb4:	39 f0       	breq	.+14     	; 0x7fc4 <verifySpace+0x14>
    7fb6:	88 e1       	ldi	r24, 0x18	; 24
    "wdr\n"
  );
}

void watchdogConfig(uint8_t x) {
  WDTCSR = _BV(WDCE) | _BV(WDE);
    7fb8:	80 93 60 00 	sts	0x0060, r24
    7fbc:	88 e0       	ldi	r24, 0x08	; 8
  WDTCSR = x;
    7fbe:	80 93 60 00 	sts	0x0060, r24
    7fc2:	ff cf       	rjmp	.-2      	; 0x7fc2 <verifySpace+0x12>

void verifySpace() {
  if (getch() != CRC_EOP) {
    watchdogConfig(WATCHDOG_16MS);    // shorten WD timeout
    while (1)			      // and busy-loop so that WD causes
      ;				      //  a reset and app start.
    7fc4:	84 e1       	ldi	r24, 0x14	; 20
  }
  putch(STK_INSYNC);
    7fc6:	df cf       	rjmp	.-66     	; 0x7f86 <putch>

00007fc8 <getNch>:
    ::[count] "M" (UART_B_VALUE)
  );
}
#endif

void getNch(uint8_t count) {
    7fc8:	cf 93       	push	r28
    7fca:	c8 2f       	mov	r28, r24
  do getch(); while (--count);
    7fcc:	e3 df       	rcall	.-58     	; 0x7f94 <getch>
    7fce:	c1 50       	subi	r28, 0x01	; 1
    7fd0:	e9 f7       	brne	.-6      	; 0x7fcc <getNch+0x4>
    7fd2:	cf 91       	pop	r28
  verifySpace();
}
    7fd4:	ed cf       	rjmp	.-38     	; 0x7fb0 <verifySpace>

00007fd6 <watchdogConfig>:
    "wdr\n"
  );
}

void watchdogConfig(uint8_t x) {
  WDTCSR = _BV(WDCE) | _BV(WDE);
    7fd6:	e0 e6       	ldi	r30, 0x60	; 96
    7fd8:	f0 e0       	ldi	r31, 0x00	; 0
    7fda:	98 e1       	ldi	r25, 0x18	; 24
    7fdc:	90 83       	st	Z, r25
  WDTCSR = x;
    7fde:	80 83       	st	Z, r24
    7fe0:	08 95       	ret

00007fe2 <appStart>:

void appStart(uint8_t rstFlags) {
  // save the reset flags in the designated register
  //  This can be saved in a main program by putting code in .init0 (which
  //  executes before normal c init code) to save R2 to a global variable.
  __asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));
    7fe2:	28 2e       	mov	r2, r24
    "wdr\n"
  );
}

void watchdogConfig(uint8_t x) {
  WDTCSR = _BV(WDCE) | _BV(WDE);
    7fe4:	e0 e6       	ldi	r30, 0x60	; 96
    7fe6:	f0 e0       	ldi	r31, 0x00	; 0
    7fe8:	88 e1       	ldi	r24, 0x18	; 24
    7fea:	80 83       	st	Z, r24
  WDTCSR = x;
    7fec:	10 82       	st	Z, r1
  //  This can be saved in a main program by putting code in .init0 (which
  //  executes before normal c init code) to save R2 to a global variable.
  __asm__ __volatile__ ("mov r2, %0\n" :: "r" (rstFlags));

  watchdogConfig(WATCHDOG_OFF);
  __asm__ __volatile__ (
    7fee:	ee 27       	eor	r30, r30
    7ff0:	ff 27       	eor	r31, r31
    7ff2:	09 94       	ijmp
